IP Library › Granted Patent US 12,340,093
Granted Patent B2
US 12,340,093 · App. 18/336,015 · Granted Jun 24, 2025

Memory system and operating method for multi-plane program thereof

Inventors: Kwang Hun Lee (Gyeonggi-do, KR); Ye Rin Kim (Gyeonggi-do, KR); Bu Yong Song (Gyeonggi-do, KR); Jae Gwan Kim (Gyeonggi-do, KR); Dong Young Seo (Gyeonggi-do, KR); Won Jun Choi (Gyeonggi-do, KR)
Assignee: SK hynix Inc.
G06F3/0619G06F3/064G06F3/0659G06F3/0679G06F12/10
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Quick Facts
Patent No.
US 12,340,093
App. No.
18/336,015
Granted
Jun 24, 2025
Kind
B2
Abstract

A memory system includes a memory device including a plurality of planes each including a plurality of memory blocks; and a memory controller for controlling the memory device to perform an operation on target blocks among the plurality of memory blocks, to store, in a replacement block, data stored in a bad block, on which the operation fails among the target blocks, and control the memory device to temporarily store, in a backup block, data stored in the other blocks except the bad block among the target blocks according to a number of free blocks included in the memory device.

Claims (35)

1. A memory system comprising:

a memory device including a plurality of planes each including memory blocks, the memory device configured to perform an operation on target blocks among a plurality of memory blocks which are included in the plurality of planes; and

a memory controller configured to:

control the memory device to perform operations on the plurality of planes simultaneously or in parallel,

store data stored in a bad block in a replacement block which is allocated to a normal area and included in a plane including the bad block, on which the operation fails among the target blocks, and

control the memory device to temporarily store, in a backup block which is allocated to an over-provisioning area and included in the plane, data stored in the other blocks except the bad block among the target blocks when a number of free blocks included in the memory device is equal to or greater than a reference value.

2. The memory system of claim 1 , wherein the operation is one of a program operation, a read operation, and an erase operation.

3. The memory system of claim 2 , wherein the target blocks are included in each of the plurality of planes included in the memory device.

4. The memory system of claim 3 , wherein the memory controller includes:

a bad block manager configured to control the memory device to store the data stored in the bad block in the replacement block and configured to generate an error occurrence signal after controlling the memory device to store data in the bad block in the replacement block;

a status controller configured to generate status information on a number of free blocks among the plurality of memory blocks and whether the number of free blocks is equal to or greater than the reference value;

an operation controller configured to control, based on the status information, the memory device to perform a reprogram operation of storing the data stored in the backup block in the other blocks; and

an address updater configured to update, when the data stored in the bad block is stored in the replacement block, mapping information including an physical address of the replacement block and a logical address provided by a host.

5. The memory system of claim 4 , wherein the operation controller controls, when the number of free blocks is equal to or greater than the reference value, the memory device to store, in the backup block, the data stored in the other blocks based on the error occurrence signal.

6. The memory system of claim 5 , wherein the operation controller is further configured to control, when the data stored in the other blocks is stored in the backup block, the memory device to perform an erase operation on the other blocks.

7. The memory system of claim 4 , wherein the operation controller controls the memory device to perform the reprogram operation simultaneously on the other blocks.

8. The memory system of claim 3 , wherein the program operation is simultaneously performed on the target blocks based on one program command provided by a host.

9. The memory system of claim 4 , wherein the bad block manager is further configured to control, when the data stored in the bad block is stored in the replacement block, the memory device to erase the data stored in the bad block.

10. The memory system of claim 9 , wherein the address updater is further configured to designate, when the data stored in the bad block is erased, the erased bad block as a new replacement block.

11. The memory system of claim 1 , wherein the replacement block is allocated to each of the plurality of planes.

12. The memory system of claim 1 , wherein the memory controller controls the memory device to store the data temporarily stored in the backup block in another memory block in the plurality of planes.

13. A method of operating a memory system, the method comprising:

controlling a memory device to perform an operation on target blocks among a plurality of memory blocks included in a plurality of planes;

controlling the memory device to store data stored in a bad block in a replacement block which is allocated to a normal area and included in a plane including the bad block, on which the operation fails among the target blocks; and

controlling the memory device to temporarily store, in a backup block which is allocated to an over-provisioning area and included in the plane, data stored in the other blocks except the bad block among the target blocks when a number of free blocks included in the memory device is equal to or greater than a reference value.

14. The method of claim 13 , wherein the controlling the memory device to store the data in the replacement block includes:

updating mapping information between an address of the replacement block and a logical address provided by a host; and

designating the bad block, which is erased, as a new replacement block.

15. The method of claim 13 , further comprising:

controlling, when the number of free blocks is equal to or greater than the reference value, the memory device to perform an erase operation on the other blocks; and

programming, in the erased blocks, the data stored in the backup block.

16. The method of claim 13 ,

wherein the operation is one of a program operation, a read operation, and an erase operation, and

wherein, in the program operation, the data is simultaneously stored in the target blocks, based on one program command provided by a host.

17. The method of claim 13 , further comprising storing, after the temporarily storing, the data stored in the backup block in another memory block included in the plurality of planes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2023
From: LEE, KWANG HUN; KIM, YE RIN; SONG, BU YONG; KIM, JAE GWAN; SEO, DONG YOUNG; CHOI, WON JUN
To: SK HYNIX INC.
Reel/Frame 063968/0530 →
Priority Claims (1)
KR 10-2022-0174308 · Dec 14, 2022 · national
Continuity (1)
Related Publication 20240201865A1 · Jun 20, 2024
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