Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks
Embodiments of instructions are detailed herein including one or more of 1) a branch fence instruction, prefix, or variants (BFENCE); 2) a predictor fence instruction, prefix, or variants (PFENCE); 3) an exception fence instruction, prefix, or variants (EFENCE); 4) an address computation fence instruction, prefix, or variants (AFENCE); 5) a register fence instruction, prefix, or variants (RFENCE); and, additionally, modes that apply the above semantics to some or all ordinary instructions.
1. An apparatus to protect against side-channel attacks that rely on a form of speculative execution, and measurement of side effects, to reveal secret data, the apparatus comprising:
a decoder to decode instructions that reference different types of registers, including packed data registers, and general-purpose registers, the instructions including a plurality of memory access instructions, the plurality of memory access instructions including load instructions to cause the apparatus to load operands from memory, and a-store instructions to cause the apparatus to store operands to the memory;
a plurality of registers to store at least some operands loaded from the memory;
scheduling circuitry to schedule the instructions for out-of-order execution;
execution circuitry to execute the instructions, the execution circuitry including a memory access circuit to access the memory in conjunction with performance of the load instruction and the store instruction, wherein the apparatus supports the form of speculative execution
that allows execution of a second instruction speculatively prior to computation of an address to be accessed by a first memory access instruction of the plurality of memory access instructions when the second instruction is after the first memory access instruction in an instruction stream;
a plurality of caches at a plurality of different levels, the plurality of caches to cache data loaded from the memory; and
circuitry to control use of the form of speculative execution to ensure the address to be accessed by the first memory access instruction prior to the execution of the second instruction, when an architectural extension is enabled by a bit in a register bit field.
2. The apparatus of claim 1 , wherein when the architectural extension is enabled the circuitry is to apply an address computation fence as part of performing an ordinary instruction.
3. The apparatus of claim 1 , further comprising:
branch prediction circuitry to predict outcomes of subsequent branch instructions based on branch prediction context established by preceding branch instructions in the instruction stream; and
second circuitry to prevent branch prediction context established by the preceding branch instructions of an indirect type from influencing prediction of outcomes of the subsequent branch instructions of an indirect type, when a second architectural extension is enabled by a second bit in a second register bit field.
4. The apparatus of claim 1 , wherein the decoder is further to decode an LFENCE instruction, a cache flush instruction, and a WBINVLD instruction.
5. The apparatus of claim 1 , wherein the form of speculative execution allows execution of a load instruction as the second instruction speculatively prior to computation of the address to be accessed by a store instruction as the first memory access instruction when the load instruction is after the store instruction in the instruction stream, and wherein the circuitry is to control the use of the form of speculative execution to ensure the address to be accessed by the store instruction is computed prior to the execution of the load instruction, when the first architectural extension is enabled.
6. The apparatus of claim 1 , wherein the circuitry is to apply an address computation fence to ensure the address to be accessed by the first memory access instruction is computed prior to the execution of the second instruction.
7. The apparatus of claim 3 , further comprising a non-transitory machine readable storage medium storing instructions that when performed by the circuitry cause the circuitry to said ensure the address to be accessed by the first memory access instruction is computed prior to the execution of the second instruction, when the first architectural extension is enabled.