Method and system for microarchitecture-aware program sampling
This application describes methods, systems, and apparatus, including computer programs encoded on computer storage media, for microarchitecture-aware program sampling. An exemplary method includes receiving one or more traces collected from one or more microarchitectures executing a computer program for evaluating hardware configurations; training a machine learning (ML) model with multi-task learning based on the one or more traces as one or more training tasks; generating a plurality of embedded vectors representing the computer program; and updating, based on the trained ML model, the plurality of embedded vectors.
1. A computer-implemented method for sampling sections of a computer program to evaluate a hardware configuration to be deployed onto a plurality of variant microarchitectures, comprising:
obtaining a plurality of traces collected from executing the computer program on the plurality of variant microarchitectures, wherein the computer program comprises a benchmark program, and each of the plurality of traces includes a plurality of performance measurements associated with one or more labels corresponding to the plurality of variant microarchitectures;
training a machine learning (ML) model with multi-task learning based on the plurality of traces and the one or more labels as one or more training tasks, wherein the ML model comprises an embedding layer trained for embedding microarchitecture-specific features of the plurality of variant microarchitectures into vector representations of the plurality of traces;
compiling the computer program into intermediate code and executable code;
obtaining an execution trace by executing the executable code on a runtime system;
inputting the intermediate code into a graph neural network (GNN) to map the intermediate code into a graph;
generating a plurality of embedded vectors based on (1) the graph and (2) the execution trace, the plurality of embedded vectors corresponding to a plurality of sections of the computer program, wherein the computer program and the plurality of embedded vectors are microarchitecture-agnostic; and
updating, using the embedding layer of the trained ML model, the plurality of embedded vectors by injecting the microarchitecture-specific features of the runtime system into the plurality of embedded vectors as a basis for performing microarchitecture-aware program sampling on the computer program;
sampling the plurality of updated embedded vectors to identify a plurality of sections of the computer program that are corresponding to the plurality of variant microarchitectures; and
returning an indication of the plurality of sections of the computer program to evaluate the hardware configuration to be deployed onto the plurality of variant microarchitectures.
2. The method of claim 1 , wherein the sampling comprises:
obtaining one or more clusters of embedded vectors by performing similarity searching on the plurality of updated embedded vectors; and
sampling at least one updated embedded vectors from each of the one or more clusters.
3. The method of claim 1 , wherein the generating the plurality of embedded vectors representing the computer program is based on basic block vectorization (BBV) or deep neural network (DNN) embedding.
4. The method of claim 1 , wherein the plurality of variant microarchitectures comprises at least one of the followings: server-class CPU, desktop-class CPU, mobile-class CPU, or Internet-of-Things (IoT) CPU.
5. The method of claim 1 , wherein the ML model comprises one or more output layers respectively corresponding to the plurality of variant microarchitectures.
6. The method of claim 5 , wherein an output of the embedding layer is an input of the one or more output layers.
7. The method of claim 1 , wherein the updating, based on the trained ML model, the plurality of embedded vectors comprises:
inputting the plurality of embedded vectors into the trained ML model; and
obtaining the plurality of updated embedded vectors as outputs from the embedding layer.
8. The method of claim 1 , wherein each of the one or more traces comprises one or more performance measures for running the computer program on a corresponding microarchitecture.
9. The method of claim 8 , wherein the one or more performance measures comprise at least one of the followings: cycles per instruction (CPI), cache miss rate, or branch misprediction rate.
10. A system for sampling sections of a computer program to evaluate a hardware configuration to be deployed onto a plurality of variant microarchitectures, the system comprising one or more processors and one or more non-transitory computer-readable memories coupled to the one or more processors, the one or more non-transitory computer-readable memories storing instructions that, when executed by the one or more processors, cause the system to perform operations comprising:
obtaining a plurality of traces collected from executing the computer program on the plurality of variant microarchitectures, wherein the computer program comprises a benchmark program, and each of the plurality of traces includes a plurality of performance measurements associated with one or more labels corresponding to the plurality of variant microarchitectures;
training a machine learning (ML) model with multi-task learning based on the plurality of traces and the one or more labels as one or more training tasks, wherein the ML model comprises an embedding layer trained for embedding microarchitecture-specific features of the plurality of variant microarchitectures into vector representations of the plurality of traces;
compiling the computer program into intermediate code and executable code;
obtaining an execution trace by executing the executable code on a runtime system;
inputting the intermediate code into a graph neural network (GNN) to map the intermediate code into a graph;
generating a plurality of embedded vectors based on (1) the graph and (2) the execution trace, the plurality of embedded vectors corresponding to a plurality of sections of the computer program, wherein the computer program and the plurality of embedded vectors are microarchitecture-agnostic; and
updating, using the embedding layer of the trained ML model, the plurality of embedded vectors by injecting the microarchitecture-specific features of the runtime system into the plurality of embedded vectors as a basis for performing microarchitecture-aware program sampling on the computer program;
sampling the plurality of updated embedded vectors to identify a plurality of sections of the computer program that are corresponding to the plurality of variant microarchitectures; and
returning an indication of the plurality of sections of the computer program to evaluate the hardware configuration to be deployed onto the plurality of variant microarchitectures.
11. The system of claim 10 , wherein the sampling comprises:
obtaining one or more clusters of embedded vectors by performing similarity searching on the plurality of updated embedded vectors; and
sampling at least one updated embedded vectors from each of the one or more clusters.
12. A non-transitory computer-readable storage medium for sampling sections of a computer program to evaluate a hardware configuration to be deployed onto a plurality of variant microarchitectures, the storage medium configured with instructions executable by one or more processors to cause the one or more processors to perform operations comprising:
obtaining a plurality of traces collected from executing the computer program on the plurality of variant microarchitectures, wherein the computer program comprises a benchmark program, and each of the plurality of traces includes a plurality of performance measurements associated with one or more labels corresponding to the plurality of variant microarchitectures;
training a machine learning (ML) model with multi-task learning based on the plurality of traces as one or more training tasks, wherein the ML model comprises an embedding layer trained for embedding microarchitecture-specific features of the plurality of variant microarchitectures into vector representations of the plurality of traces;
compiling the computer program into intermediate code and executable code;
obtaining an execution trace by executing the executable code on a runtime system;
inputting the intermediate code into a graph neural network (GNN) to map the intermediate code into a graph;
generating a plurality of embedded vectors based on (1) the graph and (2) the execution trace, the plurality of embedded vectors corresponding to a plurality of sections of the computer program, wherein the computer program and the plurality of embedded vectors are microarchitecture-agnostic; and
updating, using the embedding layer of the trained ML model, the plurality of embedded vectors by injecting the microarchitecture-specific features of the runtime system into the plurality of embedded vectors as a basis for performing microarchitecture-aware program sampling on the computer program;
sampling the plurality of updated embedded vectors to identify a plurality of sections of the computer program that are corresponding to the plurality of variant microarchitectures; and
returning an indication of the plurality of sections of the computer program to evaluate the hardware configuration to be deployed onto the plurality of variant microarchitectures.