Low noise gate driver circuits

1. A gate driver circuit, comprising:

a charge pump circuit having a charge pump output;

a first transistor having a first current terminal, a second current terminal, and a first control terminal, in which the first current terminal is coupled to the charge pump output;

a first resistor coupled between a power input terminal and the first control terminal; and

a first capacitor coupled between the first control terminal and a ground terminal, wherein the charge pump circuit includes a second capacitor having a top plate coupled to the first current terminal, and a bottom plate, a first inverter circuit including an inverter input and an inverter output coupled to the bottom plate, and a second transistor having a third current terminal coupled to the power input terminal, a fourth current terminal coupled to the inverter input, and a second control terminal coupled to the top plate.

2. The gate driver circuit of claim 1 , wherein the charge pump circuit includes a diode having:

an anode coupled to the power input terminal; and

a cathode coupled to the first current terminal.

3. The gate driver circuit of claim 1 , further comprising:

a third transistor including:

a fifth current terminal coupled to the second current terminal; and

a third control terminal; and

a second inverter circuit coupled between a gate drive enable terminal and the third control terminal.

4. The gate driver circuit of claim 1 , wherein the charge pump circuit includes:

a fourth transistor having:

a sixth current terminal coupled to the top plate;

a seventh current terminal coupled to the power input terminal; and

a fourth control terminal coupled to the fourth current terminal.

5. The gate driver circuit of claim 1 , wherein

the first inverter circuit includes:

a fifth transistor having:

an eighth current terminal coupled to the power input terminal;

a ninth current terminal coupled to the bottom plate; and

a fifth control terminal; and

a second resistor coupled between the fifth control terminal and the ground terminal.

6. The gate driver circuit of claim 5 , wherein

the first inverter circuit includes:

a sixth transistor including:

a tenth current terminal coupled to the first control terminal;

an eleventh current terminal coupled to the fifth control terminal; and

a sixth control terminal; and

a third capacitor coupled between the sixth control terminal and the power input terminal.

7. The gate driver circuit of claim 5 , wherein the first inverter circuit includes:

a seventh transistor including:

a seventh control terminal;

a twelfth current terminal coupled to the ground terminal; and

a thirteenth current terminal coupled to the sixth control terminal; and

a third resistor coupled between the sixth control terminal and the thirteenth current terminal.

8. A gate driver circuit, comprising:

a charge pump circuit having a charge pump output, the charge pump circuit configured to provide a transistor turn-on voltage at the charge pump output;

a first transistor having a first current terminal, a second current terminal, and a first control terminal, in which:

the first current terminal is coupled to the charge pump output; and

the first transistor is configured to provide the transistor turn-on voltage at the second current terminal; and

a low-pass filter circuit having a filter input and a filter output, in which:

the filter input is coupled to a power input terminal;

the filter output is coupled to the first control terminal; and

the low-pass filter circuit is configured to provide a low-pass filtered power supply voltage at the filter output,

wherein the charge pump circuit includes a capacitor having a top plate and a bottom plate, the capacitor configured to provide the transistor turn-on voltage at the top plate of the capacitor, a first inverter circuit configured to drive the bottom plate of the capacitor, and a second transistor coupled between the top plate of the capacitor and the power input terminal, the second transistor configured to discharge the capacitor.

9. The gate driver circuit of claim 8 , wherein:

the charge pump circuit includes a diode coupled between the power input terminal and the first current terminal, the diode configured to conduct a current to the first control terminal responsive to a transient on a power supply voltage at the power input terminal.

10. The gate driver circuit of claim 8 , further comprising:

a third transistor having a third current terminal, a fourth current terminal, and a second control terminal, in which:

the third current terminal is coupled to the second current terminal; and

the third transistor is configured to discharge the transistor turn-on voltage at the second current terminal; and

a second inverter circuit coupled between a gate drive enable terminal and the second control terminal.

11. The gate driver circuit of claim 8 , wherein the first inverter circuit includes:

a fourth transistor coupled between the bottom plate of the capacitor and the power input terminal, the fourth transistor configured to conduct a power supply voltage provided at the power input terminal onto the bottom plate; and

a first resistor coupled between the fourth transistor and a ground terminal, the first resistor configured to set a turn-on time of the fourth transistor.

12. The gate driver circuit of claim 11 , wherein:

the fourth transistor includes a third control terminal; and

the first inverter circuit includes:

a second resistor having a first resistor terminal and a second resistor terminal, in which the first resistor terminal is coupled to the power input terminal; and

a fifth transistor coupled between the second resistor terminal and the ground terminal.

13. A DC-DC converter, comprising:

an inductor;

a high-side transistor including:

a first current terminal coupled to a power input terminal;

a second current terminal coupled to the inductor; and

a first control terminal; and

a gate driver circuit including:

a charge pump circuit having a charge pump output;

a first transistor including:

a third current terminal coupled to the charge pump output;

a fourth current terminal coupled to the first control terminal; and

a second control terminal;

a resistor coupled between the first current terminal and the second control terminal; and

a capacitor coupled between the second control terminal and a ground terminal.

14. The DC-DC converter of claim 13 , wherein the charge pump circuit includes a diode having:

an anode coupled to the first current terminal; and

a cathode coupled to the charge pump output.

15. The DC-DC converter of claim 13 , wherein:

the capacitor is a first capacitor; and

the charge pump circuit includes:

a second capacitor having:

a top plate coupled to the third current terminal; and

a bottom plate; and

an inverter circuit having an output coupled to the bottom plate.

16. The DC-DC converter of claim 15 , wherein:

the inverter circuit includes an input; and

the charge pump circuit includes:

a second transistor having:

a fifth current terminal coupled to the first current terminal;

a sixth current terminal coupled to the input of the inverter circuit; and

a third control terminal coupled to the top plate; and

a third transistor having:

a seventh current terminal coupled to the top plate;

an eighth current terminal coupled to the first current terminal; and

a fourth control terminal coupled to the sixth current terminal.

17. The DC-DC converter of claim 15 , wherein:

the resistor is a first resistor; and

the inverter circuit includes:

a second transistor having:

a fifth current terminal coupled to the first current terminal;

a sixth current terminal coupled to the bottom plate; and

a third control terminal; and

a second resistor coupled between the third control terminal and the ground terminal.