IP Library Granted Patent US 12,341,504
Granted Patent B2
US 12,341,504 · App. 18/428,442 · Granted Jun 24, 2025

Pre-conditioning a node of a circuit

Inventors: Hamed Sadati (Swindon, GB); John A. Breslin (Glasgow, GB); Sushanth Hegde (Edinburgh, GB); John L. Melanson (Austin, TX)
Assignee: Cirrus Logic Inc.
H03K17/302H03K17/04206H03K17/063
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Quick Facts
Patent No.
US 12,341,504
App. No.
18/428,442
Granted
Jun 24, 2025
Kind
B2
Abstract

Pre-conditioning circuitry for pre-conditioning a node of a circuit to support a change in operation of the circuit, wherein the circuit is operative to change a state of the node to effect the change in operation of the circuit, and wherein the pre-conditioning circuitry is configured to apply a voltage, current or charge directly to the node to reduce the magnitude of the change to the state of the node required by the circuit to achieve the change in operation of the circuit.

Claims (11)

1. Pre-conditioning circuitry for pre-conditioning a capacitor of a circuit to support a change in operation of the circuit, wherein the pre-conditioning circuitry is configured to apply a voltage, current or charge directly to the capacitor prior to the change in operation of the circuit to reduce a settling time of the circuit following the change in operation of the circuit, wherein the pre-conditioning circuitry is configured to output a first voltage to a first circuit node and to output a second voltage to a second circuit node to pre-charge the capacitor prior to the change in operation of the circuit.

2. The pre-conditioning circuitry of claim 1 , wherein the pre-conditioning circuitry is configured to apply the voltage, current or charge directly to the capacitor to pre-charge the capacitor to a predefined level of charge prior to the change in operation of the circuit.

3. The pre-conditioning circuitry of claim 1 , wherein the pre-conditioning circuitry is configured to control a first pre-conditioning switch to selectively output the first voltage to the first circuit node and to control a second pre-conditioning switch to selectively output the second voltage to the second circuit node.

4. The pre-conditioning circuitry of claim 2 , wherein the predefined level of charge is higher than is theoretically required to achieve a given settling time.

5. The pre-conditioning circuitry of claim 4 , wherein the predefined level of charge includes an additional amount of charge to compensate for charge redistribution from the capacitor to a parasitic capacitance, an intrinsic capacitance or an explicit capacitance of the circuit.

6. The pre-conditioning circuitry of claim 1 , wherein the capacitor is a Miller capacitor.

7. The pre-conditioning circuitry of claim 1 , wherein the circuit is an amplifier circuit configured such that, in use of the amplifier circuit, the capacitor provides frequency compensation for the amplifier circuit.

8. Pre-conditioning circuitry according to claim 1 , wherein the change in operation of the circuit is in response to start-up of the circuit.

9. An integrated circuit comprising pre-conditioning circuitry according to claim 1 .

10. A host device comprising pre-conditioning circuitry according to claim 1 .

11. A host device according to claim 10 , wherein the host device comprises a laptop, notebook, netbook or tablet computer, a gaming device, a games console, a controller for a games console, a virtual reality (VR) or augmented reality (AR) device, a mobile telephone, a portable audio player, a portable device, an accessory device for use with a laptop, notebook, netbook or tablet computer, a gaming device, a games console a VR or AR device, a mobile telephone, a portable audio player or other portable device.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 4, 2025
From: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
To: CIRRUS LOGIC, INC.
Reel/Frame 070733/0367 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 5, 2024
From: SADATI, HAMED; BRESLIN, JOHN A.; HEGDE, SUSHANTH; MELANSON, JOHN L.
To: CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD.
Reel/Frame 066349/0119 →
Continuity (2)
Continuation 17356606 · Jun 24, 2021
Related Publication 20240380396A1 · Nov 14, 2024
References Cited (9)
US 4698743A · Onodera et al. · 1987 [cited by applicant]
US 9740221B2 · Cavallini et al. · 2017 [cited by applicant]
US 11082047B2 · Zhan et al. · 2021 [cited by applicant]
US 11086343B2 · Kim · 2021 [cited by applicant]
US 11625055B2 · Azevedo et al. · 2023 [cited by applicant]
US 20050035749A1 · Bo et al. · 2005 [cited by applicant]
US 20190025861A1 · Hung et al. · 2019 [cited by applicant]
US 20200052595A1 · Oak et al. · 2020 [cited by applicant]
International Search Report and Written Opinion of the International Searching Authority, International Application No. PCT/GB2022/050771, mailed Jun. 29, 2022. [cited by applicant]