Granted Patent B2

US 12,341,515 · App. 18/450,959 · Granted Jun 24, 2025

Inventors: Siman Li (Hefei, CN); Yoonjoo Eom (Hefei, CN)

Assignee: Changxin Memory Technologies, Inc.

H03K21/02H03K3/037H03K3/86

Abstract

Claims (75)

1. A delay-locked loop, comprising:

a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal, wherein a clock cycle of the intermediate clock signal is twice a clock cycle of the input clock signal;

a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal;

a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and

a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals;

a receiving module, wherein the receiving module is configured to externally receive an initial clock signal, and output the input clock signal on the basis of the initial clock signal, wherein a clock cycle of the initial clock signal is the same as the clock cycle of the input clock signal;

wherein, a phase difference between two adjacent target clock signals in the group of target clock signals is a preset value;

wherein the preset value is 90 degrees;

the group of target clock signals comprises a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal;

clock cycles of the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal are all twice a clock cycle of the input clock signal; and the phase of the first target clock signal is the same as the phase of the synchronous clock signal.

2. The delay-locked loop of claim 1 , wherein the sampling clock signal comprises a first sampling clock signal and a second sampling clock signal, and the phase of the first sampling clock signal is reverse to the phase of the second sampling clock signal;

a clock cycle of the first sampling clock signal is the same as the clock cycle of the input clock signal; a part of a rising edge of the first sampling clock signal aligns with a rising edge of the synchronous clock signal; and the other part of the rising edge of the first sampling clock signal aligns with a falling edge of the synchronous clock signal.

3. The delay-locked loop of claim 2 , wherein the delay module comprises an adjustable delay link and a phase inverter;

the adjustable delay link is configured to receive the input clock signal and an adjustment signal, perform delay transmission on the input clock signal on the basis of the adjustment signal, and output the first sampling clock signal;

the phase inverter is configured to receive the first sampling clock signal, and output the second sampling clock signal.

4. The delay-locked loop of claim 2 , wherein the latching module is specifically configured to:

latch the synchronous clock signal by using the first sampling clock signal, and output a clock signal to be processed;

latch, by using the second sampling clock signal, the clock signal to be processed, and output the second target clock signal;

latch the second target clock signal by using the first sampling clock signal, and output the third target clock signal;

latch the third target clock signal by using the second sampling clock signal, and output the fourth target clock signal; and

latch the fourth target clock signal by using the first sampling clock signal, and output the first target clock signal.

5. The delay-locked loop of claim 4 , wherein

the latching module comprises a first latch, a second latch, a third latch, a fourth latch, and a fifth latch;

an input end of the first latch receives the synchronous clock signal, a clock end of the first latch receives the first sampling clock signal, and an output end of the first latch receives the clock signal to be processed;

an input end of the second latch receives the clock signal to be processed, a clock end of the second latch receives the second sampling clock signal, and an output end of the second latch outputs the second target clock signal;

an input end of the third latch receives the second target clock signal, a clock end of the third latch receives the first sampling clock signal, and an output end of the third latch outputs the third target clock signal;

an input end of the fourth latch receives the third target clock signal, a clock end of the fourth latch receives the second sampling clock signal, and an output end of the fourth latch outputs the fourth target clock signal;

an input end of the fifth latch receives the fourth target clock signal, a clock end of the fifth latch receives the first sampling clock signal, and an output end of the fifth latch outputs the first target clock signal.

6. The delay-locked loop of claim 1 , further comprising a control module, wherein

the control module is configured to generate a delay line control signal;

the first adjustable delay line is specifically configured to receive the delay line control signal and the intermediate clock signal, adjust and transmit the intermediate clock signal on the basis of the delay line control signal, and output the synchronous clock signal.

7. The delay-locked loop of claim 6 , wherein the first target clock signal, the second target clock signal, the third target clock signal, and the fourth target clock signal are configured to perform data sampling after passing through corresponding signal transmission paths;

the control module comprises:

a feedback module, configured to receive the intermediate clock signal, output an analog clock signal, wherein the analog clock signal is configured to simulate a waveform of the first target clock signal after passing through a signal transmission path;

a detection module, configured to receive the intermediate clock signal and the analog clock signal, perform phase detection on the intermediate clock signal and the analog clock signal, and output a phase detection signal;

a parameter adjustment module, configured to receive the phase detection signal, and output the delay line control signal on the basis of the phase detection signal.

8. The delay-locked loop of claim 7 , wherein the feedback module comprises:

a second adjustable delay line, configured to receive the delay line control signal and the intermediate clock signal, adjust and transmit the intermediate clock signal on the basis of the delay line control signal, and output a replication clock signal, wherein a structure of the second adjustable delay line is the same as a structure of the first adjustable delay line, and the replication clock signal is configured to simulate the waveform of the first target clock signal;

a replication delay module, configured to receive the replication clock signal, delay the replication clock signal, and output the analog clock signal, wherein the replication delay module is at least configured to simulate a time delay of the signal transmission path.

9. A delay locking method, comprising:

receiving an initial clock signal externally and outputting an input clock signal on the basis of the initial clock signal, wherein a clock cycle of the initial clock signal is the same as the clock cycle of the input clock signal;

receiving the input clock signal and performing frequency division on the input clock signal to obtain an intermediate clock signal, wherein a clock cycle of the intermediate clock signal is twice a clock cycle of the input clock signal;

adjusting and transmitting the intermediate clock signal through a first adjustable delay line to obtain a synchronous clock signal, and performing delay transmission on the input clock signal to obtain a sampling clock signal; and

latching the synchronous clock signal on the basis of the sampling clock signal to obtain a group of target clock signals, wherein a phase difference between two adjacent target clock signals in the group of target clock signals is a preset value.

10. A clock synchronization circuit, comprising a delay-locked loop and a data selection module, wherein a signal transmission path is arranged between the delay-locked loop and the data selection module;

wherein the delay-locked loop comprises:

a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal, wherein a clock cycle of the intermediate clock signal is twice a clock cycle of the input clock signal;

a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal;

a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and

a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals;

wherein, a phase difference between two adjacent target clock signals in the group of target clock signals is a preset value;

wherein the data selection module is configured to:

receive the group of target clock signals through the signal transmission path, and perform sampling and selective outputting on a data signal by using the group of target clock signals, so as to output a target data signal.

11. The clock synchronization circuit of claim 10 , wherein the preset value is 90 degrees;

the group of target clock signals comprises a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal;

clock cycles of the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal are all twice a clock cycle of the input clock signal; and

the phase of the first target clock signal is the same as the phase of the synchronous clock signal.

12. The clock synchronization circuit of claim 11 , wherein the sampling clock signal comprises a first sampling clock signal and a second sampling clock signal, and the phase of the first sampling clock signal is reverse to the phase of the second sampling clock signal;

a clock cycle of the first sampling clock signal is the same as the clock cycle of the input clock signal; a part of a rising edge of the first sampling clock signal aligns with a rising edge of the synchronous clock signal; and the other part of the rising edge of the first sampling clock signal aligns with a falling edge of the synchronous clock signal.

13. The clock synchronization circuit of claim 12 , wherein the delay module comprises an adjustable delay link and a phase inverter;

the adjustable delay link is configured to receive the input clock signal and an adjustment signal, perform delay transmission on the input clock signal on the basis of the adjustment signal, and output the first sampling clock signal;

the phase inverter is configured to receive the first sampling clock signal, and output the second sampling clock signal.

14. The clock synchronization circuit of claim 12 , wherein the latching module is specifically configured to:

latch the synchronous clock signal by using the first sampling clock signal, and output a clock signal to be processed;

latch, by using the second sampling clock signal, the clock signal to be processed, and output the second target clock signal;

latch the second target clock signal by using the first sampling clock signal, and output the third target clock signal;

latch the third target clock signal by using the second sampling clock signal, and output the fourth target clock signal; and

latch the fourth target clock signal by using the first sampling clock signal, and output the first target clock signal.

15. The clock synchronization circuit of claim 10 , wherein the delay-locked loop further comprises a receiving module, wherein

the receiving module is configured to externally receive an initial clock signal, and output the input clock signal on the basis of the initial clock signal, wherein a clock cycle of the initial clock signal is the same as the clock cycle of the input clock signal.

16. The clock synchronization circuit of claim 10 , wherein

the delay-locked loop is specifically configured to output a first target clock signal, a second target clock signal, a third target clock signal and a fourth target clock signal on the basis of the input clock signal, wherein phases among the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal differ by 90 degrees in turn; and

the data selection module is specifically configured to perform sampling and selective outputting on the data signal by using the first target clock signal, the second target clock signal, the third target clock signal and the fourth target clock signal, so as to obtain the target data signal.

17. A memory, comprising the clock synchronization circuit of claim 16 .

18. The memory of claim 17 , complying with DDR5 specification.

Assignments (2)

Priority Claims (1)

Continuity (2)

References Cited (35)