System with a low-drift on-chip oscillator with lowered sensitivity to random telegraph noise
A system with a low-drift on-chip (LD-RC) oscillator with lowered sensitivity to Random Telegraph Noise when generating a current (Id) for the LD-RC oscillator. A control resistor (R) is connected through an intermediary arrangement to one of a first MOS transistor (M 1 ) or of a second MOS transistor (M 2 ) between two terminals of a supply voltage source (Vdd). The gate of the first MOS transistor (M 1 ) is connected to the gate of the second MOS transistor (M 2 ), whereas the source of the first MOS transistor (M 1 ) and the source of the second MOS transistor (M 2 ) are connected to one terminal of the supply voltage source (Vdd), the control resistor (R) being connected to the other opposite terminal of the supply voltage source.
1. A system with a low-drift on-chip oscillator with lowered sensitivity to Random Telegraph Noise, for generating a current (Id) in operation for the LD-RC oscillator, said system comprising a control resistor (R) connected through an intermediary arrangement to one of a first MOS transistor (M 1 ) or of a second MOS transistor (M 2 ) between two terminals of a supply voltage source (Vdd), the gate of the first MOS transistor (M 1 ) is connected to the gate of the second MOS transistor (M 2 ), whereas the source of the first MOS transistor (M 1 ) and the source of the second MOS transistor (M 2 ) are connected in direction to a first terminal of the supply voltage source (Vdd), the control resistor (R) being connected to a second terminal opposite to the first terminal of the supply voltage source, and the system comprising still a feedback unit, which is an operational amplifier for a comparison of a voltage (Vr) generated by a current (Is) through the control resistor R and a supply voltage (Vc) generated by the current (Id) through the LD-RC oscillator, an output (VrP) of the operational amplifier being connected to gates of the first and second MOS transistors (M 1 , M 2 ),
the intermediary arrangement including chopping switches (S 1 A, S 1 B, S 2 B, S 2 A) controlled by a switch control unit which is intended to be clocked by the frequency signal (F 0 ) of the LD-RC oscillator in operation and placed between the control resistor (R) and the first and second MOS transistors (M 1 , M 2 ), and between the LD-RC oscillator and the first and second MOS transistors (M 1 , M 2 ), a first controlled chopping switch (S 1 A) being placed between the control resistor (R) and the drain of the first MOS transistor (M 1 ) of a first branch, whereas a second controlled chopping switch (S 1 B) is placed between the LD-RC oscillator and the drain of the second MOS transistor (M 2 ) of a second branch,
a third controlled chopping switch (S 2 B) being placed between the control resistor (R) and the drain of the second MOS transistor (M 2 ), whereas a fourth controlled chopping switch (S 2 A) is placed between the LD-RC oscillator and the drain of the first MOS transistor (M 1 ),
the first and second switches (S 1 A, S 1 B) being intended to be controlled by a first control signal (PH 1 ) from the switch control unit intended to be in conducting mode during a first phase P 1 , whereas the third and fourth switches (S 2 B, S 2 A) are intended to be controlled by a second control signal (PH 2 ) from the switch control unit intended to be in non-conductive mode during the first phase P 1 , and
the third and fourth switches (S 2 B, S 2 A) being intended to be controlled by the second control signal (PH 2 ) intended to be in conducting mode during a second phase P 2 , whereas the first and second switches (S 1 A, S 1 B) are intended to be controlled by the first control signal (PH 1 ) intended to be in non-conductive mode during the second phase P 2 ,
wherein the LD-RC oscillator is a ring oscillator having an odd number n of inverters, which are connected in series to form a ring.
2. The system according to claim 1 , wherein the ring oscillator comprises three inverters connected in series, an output of the first inverter being connected to an input of the second inverter, an output of the second inverter being connected to an input of the third inverter, and an output of the third inverter being connected to an input of the first inverter in order to form a ring, the output of the third inverter generating the frequency signal (F 0 ), which is an oscillating signal at a frequency F 0 , and wherein the oscillating signal is a sinusoidal signal or a square signal or a triangular signal or a sawtooth signal.
3. The system according to claim 2 , wherein each inverter has an intrinsic capacitor Co, and wherein in operation, the current Id is defined by the equation: Id=F 0 ·C·Vc, with C=n·Co and Vc being the voltage across a capacitor Cc connected to the inverters and is the voltage supply for each inverter of the ring oscillator of the system with respect to the second supply terminal, and which is provided to be always active during different system intervals or times, in particular during sleep times of the system.
4. The system according to claim 1 , wherein the first and second MOS transistors (M 1 , M 2 ) are PMOS transistors with their source connected to the first terminal, which is the terminal of the supply voltage Vdd, and wherein the control resistor (R) and the LD-RC oscillator are connected to the second terminal, which is the ground.
5. The system according to claim 1 , wherein cascade MOS transistors (M 3 , M 4 ) are added and placed between the arrangement of controlled chopping switches (S 1 A, S 1 B, S 2 A, S 2 B), and the control resistor (R) and also the LD-RC oscillator, in that a first cascade MOS transistor (M 3 ) is connected to the resistor (R) in one side and in other side to the first and third switches (S 1 A, S 2 B), whereas a second cascade MOS transistor (M 4 ) is connected in one side to the LD-RC oscillator, and in the other side to the second and fourth switches (S 1 B, S 2 A).
6. The system according to claim 5 , wherein cascade MOS transistors (M 3 , M 4 ) are PMOS transistors, and wherein first and second MOS transistors (M 1 , M 2 ) are PMOS transistors with their source connected to the first terminal, which is the terminal of the supply voltage Vdd, whereas the control resistor (R) and the LD-RC oscillator are connected to the second terminal, which is the ground.
7. A method for lowering sensitivity to Random Telegraph Noise of a system with a low-drift on-chip oscillator in an oscillator stage for generating a current (Id) for the LD-RC oscillator, said system comprising a control resistor (R) connected through an intermediary arrangement to one of a first MOS transistor (M 1 ) or of a second MOS transistor (M 2 ) between two terminals of a supply voltage source (Vdd), the gate of the first MOS transistor (M 1 ) being connected to the gate of the second MOS transistor (M 2 ), whereas the source of the first MOS transistor (M 1 ) and the source of the second MOS transistor (M 2 ) are connected in direction to a first terminal of the supply voltage source (Vdd), the control resistor (R) being connected to a second terminal opposite to the first terminal of the supply voltage source (Vdd), and the system comprising in the oscillator stage still a feedback unit, which is an operational amplifier in operation for the comparison between a voltage (Vr) generated by a current (Is) through the control resistor R and a supply voltage (Vc) generated by the current (Id) through the LD-RC oscillator, an output (VrP) of the operational amplifier being connected to gates of the first and second MOS transistors (M 1 , M 2 ),
for implementing the method, the intermediary arrangement includes first, second, third, fourth controlled chopping switches (S 1 A, S 1 B, S 2 B, S 2 A) controlled by a switch control unit, placed between the control resistor (R) and the first and second MOS transistors (M 1 , M 2 ), and between the LD-RC oscillator and the first and second MOS transistors (M 1 , M 2 ), wherein a first controlled chopping switch (S 1 A) is placed between the control resistor (R) and the drain of the first MOS transistor (M 1 ) of a first branch, whereas a second controlled chopping switch (S 1 B) is placed between the LD-RC oscillator and the drain of the second MOS transistor (M 2 ) of a second branch, and wherein a third controlled chopping switch (S 2 B) is placed between the control resistor (R) and the drain of the second MOS transistor (M 2 ), whereas a fourth controlled chopping switch (S 2 A) is placed between the LD-RC oscillator and the drain of the first MOS transistor (M 1 ), and
the first and second switches (S 1 A, S 1 B) being controlled by a first control signal (PH 1 ) to be in conducting mode during a first phase P 1 , whereas the third and fourth switches (S 2 B, S 2 A) are controlled by a second control signal (PH 2 ) to be in non-conductive mode during the first phase P 1 ,
the third and fourth switches (S 2 B, S 2 A) being controlled by the second control signal (PH 2 ) to be in conducting mode during a second phase P 2 , whereas the first and second switches (S 1 A, S 1 B) are controlled by the first control signal (PH 1 ) intended to be in non-conductive mode during the second phase P 2 ,
all the controlled chopping switches (S 1 A, S 1 B, S 2 B, S 2 A) being controlled by the switch control unit at least during a predefined time, which is a sleep time (Tsleep), or all the time of some parts of the system other than the oscillator stage, and
during the predefined time or all the time, phases P 1 and phases P 2 alternating successively in order to perform a chopping operation by commuting the first and second MOS transistors (M 1 , M 2 ) from phase P 1 to phase P 2 , and from phase P 2 to phase P 1 ,
wherein the LD-RC oscillator is a ring oscillator having an odd number n of CMOS inverters has the balance ensured via a feedback unit, which is implemented by an operational amplifier in the depicted case.
8. The method according to claim 7 , wherein during a period corresponding to the predefined time or all the time, all the chopping switches (S 1 A, S 1 B, S 2 B, S 2 A) are commuted to pass successively from phase P 1 to phase P 2 and from phase P 2 to phase P 1 , and each phase approximately during 50% of the time by phases P 1 and 50% of time by phases P 2 .
9. The method according to claim 7 , wherein the oscillating signal (F 0 ) from the LD-RC oscillator is supplied to clock a timer of a switch logic unit to determine a sleep time before waking up all the system.