Transistor structure including oxide semiconductor pattern surrounding bottom and sidewall of gate and semiconductor device using the same
A transistor structure including an active pattern defined by a first isolation pattern on a substrate, a second isolation pattern at an upper portion of the active pattern, a gate structure extending through the active pattern and the first isolation pattern, at least a lower portion of the gate structure extending through the second isolation pattern, a first oxide semiconductor pattern on a lower surface and a sidewall of the gate structure, the first oxide semiconductor pattern including In-rich IGZO and at least partially contacting the first and second isolation patterns, and source/drain regions at upper portions of the active pattern adjacent to the gate structure may be provided.
1. A transistor structure comprising:
an active pattern defined by a first isolation pattern on a substrate;
a second isolation pattern at an upper portion of the active pattern;
a gate structure extending through the active pattern and the first isolation pattern, at least a lower portion of the gate structure extending through the second isolation pattern;
a first oxide semiconductor pattern on a lower surface and a sidewall of the gate structure, the first oxide semiconductor pattern including In-rich IGZO and at least partially contacting the first and second isolation patterns; and
source/drain regions at the upper portion of the active pattern adjacent to the gate structure.
2. The transistor structure according to claim 1 , wherein lower surfaces of the source/drain regions contact an upper surface of the second isolation pattern.
3. The transistor structure according to claim 1 , wherein the source/drain regions include doped polysilicon or doped single crystalline silicon.
4. The transistor structure according to claim 1 , wherein the source/drain regions include metal, metal nitride or metal silicide.
5. The transistor structure according to claim 1 , wherein the first isolation pattern contacts upper and lower portions of the first oxide semiconductor pattern, and the second isolation pattern contacts the lower portion of the first oxide semiconductor pattern.
6. The transistor structure according to claim 1 , wherein
the gate structure is one of a plurality of gate structures, the plurality of gate structures spaced apart from each other in a first direction, each of the plurality of gate structures extending in a second direction and crossing the first direction, the first direction and the second direction being substantially parallel to an upper surface of the substrate,
the active pattern is one of a plurality of active patterns, the plurality of active patterns spaced apart from each other in the second direction and in a third direction, the third direction parallel to the upper surface of the substrate and having an acute angle with respect to the second direction, each of the plurality of active patterns extending in the third direction to a given length, and
two gate structures of the plurality of gate structures neighboring in the first direction extended through each of the plurality of active patterns.
7. The transistor structure according to claim 6 , wherein
the source/drain regions include first, second and third source/drain regions arranged in order in the third direction, the first, second, and third source/drain regions being at the upper portion of the active pattern, the upper portions of the active pattern being adjacent to the two gate structures, and
the transistor structure further comprises a second oxide semiconductor pattern on a sidewall of each of the first and third source/drain regions, the second oxide semiconductor pattern including Ga-rich IGZO.
8. The transistor structure according to claim 7 , wherein the second oxide semiconductor pattern directly contacts the sidewall of each of the first and third source/drain regions.
9. The transistor structure according to claim 7 , further comprising:
a third isolation pattern between the second oxide semiconductor pattern and the active pattern.
10. The transistor structure according to claim 9 , wherein the third isolation pattern directly contacts the sidewall of each of the first and third source/drain regions.
11. A transistor structure comprising:
an active pattern defined by an isolation pattern on a substrate, the active pattern including IGZO;
a gate structure extending through the active pattern and the isolation pattern;
a first oxide semiconductor pattern on a sidewall of a portion of the active pattern adjacent to the isolation pattern, the first oxide semiconductor pattern including Ga-rich IGZO; and
source/drain regions at an upper portion of the active pattern adjacent to the gate structure.
12. The transistor structure according to claim 11 , further comprising:
a second oxide semiconductor pattern on a lower surface and a lower sidewall of a portion of the gate structure extending through the active pattern, the second oxide semiconductor pattern including In-rich IGZO.
13. The transistor structure according to claim 11 , wherein the active pattern includes In-rich IGZO.
14. The transistor structure according to claim 11 , wherein lower surfaces of the source/drain regions contact corresponding portions, respectively, of an upper surface of the first oxide semiconductor pattern.
15. The transistor structure according to claim 11 , wherein the source/drain regions include metal, metal nitride or metal silicide.
16. A semiconductor device comprising:
an active pattern defined by a first isolation pattern on a substrate;
a second isolation pattern at an upper portion of the active pattern;
a gate structure extending through the active pattern and the first isolation pattern, at least a lower portion of the gate structure extending through the second isolation pattern in a first direction, the first direction being substantially parallel to an upper surface of the substrate;
a first oxide semiconductor pattern on a lower surface and a sidewall of the gate structure, the first oxide semiconductor pattern including In-rich IGZO and at least partially contacting the first and second isolation patterns;
source/drain regions at the upper portion of the active pattern adjacent to the gate structure;
a bit line structure on one of the source/drain regions and extending in a second direction, the second direction being substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction;
a spacer structure on a sidewall of the bit line structure;
a contact plug structure on one of the source/drain regions; and
a capacitor on the contact plug structure.
17. The semiconductor device according to claim 16 , wherein:
the gate structure is one of a plurality of gate structures spaced apart from each other in the second direction,
the active pattern is one of a plurality of active patterns spaced apart from each other in the first direction and in a third direction, the third direction substantially parallel to the upper surface of the substrate and having an acute angle with respect to the first direction, each of the plurality of active patterns extending in the third direction to a given length, and
two gate structures of the plurality of gate structures neighboring in the second direction extend through each of the plurality of active patterns.
18. The semiconductor device according to claim 17 , wherein:
the source/drain regions include first, second and third source/drain regions arranged in order in the third direction, the first, second and third source/drain regions being at the upper portion of the active pattern adjacent to the two gate structures,
the bit line structure is on the second source/drain region,
the contact plug structure is on each of the first and third source/drain regions, and
the semiconductor device further comprises a second oxide semiconductor pattern on a sidewall of each of the plurality of active patterns under the first and third source/drain regions, the second oxide semiconductor pattern including Ga-rich IGZO.
19. The semiconductor device according to claim 18 , wherein the second oxide semiconductor pattern directly contacts a sidewall of each of the first and third source/drain regions.
20. The semiconductor device according to claim 18 , further comprising:
a third isolation pattern between the second oxide semiconductor pattern and the active pattern.