Photonics chips with thermal management for a cavity-mounted chip
Structures for a cavity-mounted chip and methods of fabricating a structure for a cavity-mounted chip. The structure comprises a substrate including a cavity, a thermoelectric device inside the cavity, and a chip disposed inside the cavity adjacent to the thermoelectric device. The thermoelectric device includes a first plurality of pillars and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit, the first plurality of pillars comprising an n-type semiconductor material, and the second plurality of pillars comprising a p-type semiconductor material.
1. A structure comprising:
a substrate including a cavity;
a first thermoelectric device inside the cavity, the first thermoelectric device including a first dielectric layer, a second dielectric layer, a plurality of connectors, a first plurality of pillars, and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit, the plurality of connectors coupling the first plurality of pillars to the second plurality of pillars in the series circuit, the first plurality of pillars and the second plurality of pillars disposed between the first dielectric layer and the second dielectric layer, the first plurality of pillars comprising an n-type semiconductor material, and the second plurality of pillars comprising a p-type semiconductor material; and
a chip disposed inside the cavity adjacent to the first thermoelectric device,
wherein the first dielectric layer includes an opening exposing a portion of one of the plurality of connectors.
2. The structure of claim 1 wherein the chip comprises a laser diode.
3. The structure of claim 2 further comprising:
a waveguide core including a tapered section disposed adjacent to the laser diode,
wherein the tapered section of the waveguide core is configured to receive light from the laser diode.
4. The structure of claim 1 wherein the substrate has a top surface, the cavity has a floor and a plurality of sidewalls extending from the floor to the top surface of the substrate, the chip includes a body having a bottom surface, and the first thermoelectric device is disposed between the floor of the cavity and the bottom surface of the body of the chip.
5. The structure of claim 4 wherein the first dielectric layer and the second dielectric layer are spaced from at least one of the plurality of sidewalls by a gap.
6. The structure of claim 1 wherein the first thermoelectric device is disposed inside a first portion of the cavity, and further comprising:
a second thermoelectric device disposed inside a second portion of the cavity.
7. The structure of claim 1 wherein the n-type semiconductor material comprises bismuth telluride doped with selenium, and the p-type semiconductor material comprises bismuth telluride doped with antimony.
8. The structure of claim 1 wherein the chip is disposed over the first dielectric layer.
9. The structure of claim 1 wherein the first thermoelectric device includes a third dielectric layer between the first dielectric layer and the second dielectric layer, the first plurality of pillars and the second plurality of pillars are disposed in the third dielectric layer, and the plurality of connectors are disposed between the first dielectric layer and the second dielectric layer.
10. A structure comprising:
a substrate including a cavity;
a thermoelectric device inside the cavity, the thermoelectric device including a first dielectric layer, a second dielectric layer, a plurality of connectors, a first plurality of pillars, and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit, the plurality of connectors coupling the first plurality of pillars to the second plurality of pillars in the series circuit, the first plurality of pillars and the second plurality of pillars disposed between the first dielectric layer and the second dielectric layer, the first plurality of pillars comprising an n-type semiconductor material, and the second plurality of pillars comprising a p-type semiconductor material;
a chip disposed inside the cavity adjacent to the thermoelectric device,
a contact via that extends through the first dielectric layer to a portion of one of the plurality of connectors; and
a pad coupled to the contact via.
11. The structure of claim 10 wherein the chip includes a through-silicon via coupled to the series circuit.
12. The structure of claim 10 further comprising:
a first redistribution layer that couples the contact via to the pad.
13. The structure of claim 12 wherein the cavity has a first sidewall, and the first redistribution layer extends up the first sidewall to the pad.
14. The structure of claim 13 wherein the cavity has a second sidewall adjacent to the first sidewall, and further comprising:
a second redistribution layer that is coupled to the chip,
wherein the second redistribution layer extends up the second sidewall.
15. The structure of claim 13 wherein the cavity has a second sidewall opposite to the first sidewall, and further comprising:
a waveguide core including a tapered section disposed adjacent to the second sidewall.
16. The structure of claim 10 wherein the chip includes a body having a bottom surface and a pad at the bottom surface, and further comprising:
a redistribution layer on the first dielectric layer; and
a solder joint that couples the pad of the body to a portion of the redistribution layer.
17. The structure of claim 10 wherein the chip comprises a laser diode.
18. The structure of claim 17 further comprising:
a waveguide core including a tapered section disposed adjacent to the laser diode,
wherein the tapered section of the waveguide core is configured to receive light from the laser diode.
19. The structure of claim 10 wherein the thermoelectric device includes a third dielectric layer between the first dielectric layer and the second dielectric layer, the first plurality of pillars and the second plurality of pillars are disposed in the third dielectric layer, and the plurality of connectors are disposed between the first dielectric layer and the second dielectric layer.
20. A method comprising:
forming a cavity in a substrate;
forming a thermoelectric device inside the cavity, wherein the thermoelectric device includes a first dielectric layer, a second dielectric layer, a plurality of connectors, a first plurality of pillars, and a second plurality of pillars that alternate with the first plurality of pillars in a series circuit, the plurality of connectors couple the first plurality of pillars to the second plurality of pillars in the series circuit, the first plurality of pillars and the second plurality of pillars are disposed between the first dielectric layer and the second dielectric layer, the first plurality of pillars comprise an n-type semiconductor material, and the second plurality of pillars comprise a p-type semiconductor material; and
disposing a chip inside the cavity adjacent to the thermoelectric device,
wherein the first dielectric layer includes an opening exposing a portion of one of the plurality of connectors.