IP Library › Granted Patent US 12,346,257
Granted Patent B2
US 12,346,257 · App. 17/965,545 · Granted Jul 1, 2025

Systems and methods for processing storage transactions

Inventors: Ramdas P. Kachare (Pleasanton, CA); Jimmy Lau (Santa Clara, CA); Tinh Lac (Manteca, CA); Mounica Behara (San Jose, CA); Vinit Apte (San Jose, CA)
Assignee: Samsung Electronics Co., Ltd.
G06F12/0848G06F12/1081
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Quick Facts
Patent No.
US 12,346,257
App. No.
17/965,545
Granted
Jul 1, 2025
Kind
B2
Abstract

Systems and methods for processing storage transactions are disclosed. A transaction between a storage device and a host computing device is identified. The storage device determines that the transaction satisfies a criterion, and inserts data into a packet associated with the transaction. The data may be for identifying a memory subsystem of the host computing device. The storage device transmits the packet, including the data, to the host computing device for storing the packet in the memory subsystem based on the data.

Claims (33)

1. A method for processing storage transactions, the method comprising:

identifying a transaction between a storage device and a host computing device;

determining, by the storage device, that the transaction is for storing a packet in the host computing device;

based on determining that the transaction is for storing the packet, determining a transaction type for the transaction;

based on determining the transaction type, inserting, by the storage device, into the packet, a value selected from a first value associated with a first transaction type and a second value associated with a second transaction type, the value corresponding to a location of a memory subsystem of the host computing device; and

transmitting, by the storage device, the packet with the value inserted in the packet, to the host computing device for storing the packet in the location of the memory subsystem based on the value.

2. The method of claim 1 , wherein the transaction adheres to a storage interface protocol for transferring the packet using direct memory access, wherein the storage interface protocol is a non-volatile memory express (NVMe) protocol.

3. The method of claim 1 further comprising:

performing a write address translation based on the value.

4. The method of claim 1 , wherein the packet includes data retrieved from the storage device, or an input/output command completion related data structures.

5. The method of claim 1 , wherein the value is determined based on a parameter associated with the storage device.

6. The method of claim 5 , wherein the parameter is a status of the storage device or an identifier of a component used by the storage device.

7. The method of claim 1 , wherein the value includes bits for identifying the memory subsystem.

8. The method of claim 1 , wherein the packet is a translation layer packet (TLP), and the value includes a TLP processing hint (TPH) inserted into a header of the TLP.

9. The method of claim 1 , wherein the memory subsystem includes a portion of a cache memory.

10. A storage device comprising:

a non-volatile memory device; and

one or more embedded processors, wherein the one or more embedded processors respectively include logic for:

identifying a transaction with a host computing device;

determining that the transaction is for storing a packet in the host computing device;

based on determining that the transaction is for storing the packet, inserting into the packet, a value corresponding to a location of a memory subsystem of the host computing device; and

transmitting the packet with the value inserted in the packet, to the host computing device, wherein the host computing device is configured to:

retrieve the value inserted in the packet; and

identify the location of the memory subsystem based retrieving the value from the packet; and

store the packet into the location of the memory subsystem.

11. The storage device of claim 10 , wherein the transaction adheres to a storage interface protocol for transferring the packet using direct memory access, wherein the storage interface protocol is a non-volatile memory express (NVMe) protocol.

12. The storage device of claim 10 , wherein the one or more embedded processors include logic for performing a write address translation based on the value.

13. The storage device of claim 10 , wherein the packet includes data retrieved from the storage device, or an input/output command completion related data structures.

14. The storage device of claim 10 , wherein the value is determined based on a parameter associated with the storage device.

15. The storage device of claim 14 , wherein the parameter is a status of the storage device or an identifier of a component used by the storage device.

16. The storage device of claim 10 , wherein the value includes bits for identifying the memory subsystem.

17. The storage device of claim 10 , wherein the packet is a translation layer packet (TLP), and the value includes a TLP processing hint (TPH) inserted into a header of the TLP.

18. The storage device of claim 10 , wherein the memory subsystem includes a portion of a cache memory.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 21, 2024
From: KACHARE, RAMDAS P.; LAU, JIMMY; LAC, TINH; BEHARA, MOUNICA; APTE, VINIT
To: SAMSUNG ELECTRONICS CO., LTD.
Reel/Frame 066862/0164 →
Continuity (2)
Provisional Application 63404474 · Sep 7, 2022
Related Publication 20240078183A1 · Mar 7, 2024
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