Semiconductor device and system including the same
A semiconductor device includes: a plurality of ports exchanging data with each other in an interface; and an interface controller including a link training and status state machine (LTSSM), configured to execute link-up, setting a plurality of lanes to the plurality of ports, and a memory configured to store a sequence, in which the LTSSM succeeding in the link-up executes states, as a reference sequence. The interface controller changes at least one of the PHY parameters when a calibration operation of adjusting the PHY parameters starts until a sequence of the states, executed by the LTSSM to complete the link-up, matches the reference sequence.
1. A semiconductor device comprising:
a plurality of ports configured for exchanging data with each other in an interface; and
an interface controller including a link training and status state machine (LTSSM) and a memory,
wherein the LTSSM is configured to execute link-up by executing a sequence of states that succeeds in setting a plurality of lanes to the plurality of ports,
wherein the memory is configured to store the sequence of states that succeeds as a reference sequence,
wherein the interface controller changes at least one of the PHY parameters when a calibration operation of adjusting the PHY parameters starts until a sequence of the states, executed by the LTSSM to complete the link-up, matches the reference sequence.
2. The semiconductor device of claim 1 , wherein: the interface controller is configured to perform the calibration operation whenever power is turned on again after the power is turned off.
3. The semiconductor device of claim 1 , wherein:
the interface is a Peripheral Component Interconnect Express (PCIe) interface,
the interface controller is a PCIe controller configured to re-perform the calibration operation when a predetermined reference time elapses after the LTSSM succeeds in link-up.
4. The semiconductor device of claim 3 , wherein:
the PCIe controller performs the calibration operation after waiting until transmission of data is completed when the data is transmitted in at least one of the plurality of ports at a time point at which the reference time elapses.
5. The semiconductor device of claim 3 , wherein:
the PCIe controller performs the calibration operation when a state of the LTSSM transitions to an L0s state or an L1 state after the reference time elapses.
6. The semiconductor device of claim 1 , wherein:
the interface controller performs the calibration operation when receiving a request from a user.
7. The semiconductor device of claim 1 , wherein:
each of the plurality of ports is connected to a transmitter and a receiver; and
a setting of at least one of the transmitter and the receiver, connected to at least of the plurality of ports, is changed when the interface controller adjusts the PHY parameters.
8. The semiconductor device of claim 7 , wherein:
at least one of a level, a slew rate, and a frequency of a signal, output by the transmitter or received by the receiver, is changed.
9. The semiconductor device of claim 1 , wherein:
at least one of the states, executed by the LTSSM, includes two or more sub-states; and
the reference sequence includes a sequence in which the LTSSM succeeding in the link-up executes the sub-states.
10. The semiconductor device of claim 1 , wherein:
the reference sequence includes a Detect state, a Polling state, a Configuration state, and an L0 state, a normal operation state, in order.
11. A semiconductor device comprising:
a plurality of ports exchanging data with each other under an interface environment; and
an interface controller including a link training and status state machine (LTSSM) and a memory,
wherein the LTSSM is configured to execute link-up by executing a sequence of states that succeeds in setting a plurality of lanes to the plurality of ports,
wherein the memory is configured to store the sequence of states that succeeds as a reference sequence,
wherein the interface controller changes at least one PHY parameter, among PHY parameters determining characteristics of signals input to the plurality of ports and output from the plurality of ports, at each of a first time point and a second time point subsequent to an operation start time point at which the plurality of ports are connected to an external device and receive power.
12. The semiconductor device of claim 11 , wherein:
the interface controller receives a built-in self-calibration (BISC) request from a user at a time point between the first time point and the second time point.
13. The semiconductor device of claim 11 , wherein:
the interface controller changes at least one of the PHY parameters when a predetermined reference time has elapsed from the operation start time point; and
the reference time is shorter than a time from the operation start time point to the first time point.
14. The semiconductor device of claim 11 , wherein:
the interface controller changes at least one of the PHY parameters and tries link-up with the external device using the LTSSM; and
the interface controller changes at least one of the PHY parameters until a sequent of states, executed by the LTSSM to complete the link-up with the external device, matches the reference sequence.
15. The semiconductor device of claim 11 , wherein:
the memory stores a plurality of reference sequences classified depending on at least one of a type of the external device, an external temperature, and a magnitude of the power.
16. The semiconductor device of claim 15 , wherein:
the interface controller is a Peripheral Component Interconnect Express (PCIe) controller,
the PCIe controller selects at least one of the plurality of reference sequences based on at least one of the external temperature and the magnitude of the power at each of the first time point and the second time point, and
the PCIe controller changes at least one of the PHY parameters until a sequence of states, executed by the LTSSM to complete the link-up with external device, matches the selected reference sequence.
17. A system comprising:
a first semiconductor device including a first interface and a first interface controller configured to control the first interface;
a second semiconductor device including a second interface and a second interface controller configured to control the second interface; and
a third semiconductor device including a third interface, connected to the first interface, and a fourth interface connected to the second interface,
wherein the first interface controller changes at least one PHY parameter, among PHY parameters of the first interface, at a first time point and reconfigures a link between the first interface and the third interface,
wherein the second interface controller changes at least one PHY parameter, among PHY parameters of the second interface, at a second time point, different from the first time point, and reconfigures a link between the second interface and the fourth interface,
wherein at least one of the first semiconductor device or the second semiconductor device includes a link training and status state machine (LTSSM) and a memory,
wherein the LTSSM is configured to execute link-up by executing a sequence of states that succeeds in setting a plurality of lanes to a plurality of ports,
wherein the memory is configured to store the sequence of states that succeeds as a reference sequence.
18. The system of claim 17 , wherein:
at least one of the first interface controller or the second interface controller is a Peripheral Component Interconnect Express (PCIe) controller,
the third semiconductor device is a host device, and the first semiconductor device and the second semiconductor device perform different functions.
19. The system of claim 17 ,
wherein each of the first semiconductor device and the second semiconductor device includes an LTSSM and a memory,
wherein each LTSSM is configured to execute link-up by executing a sequence of states that succeeds in setting a plurality of lanes to a plurality of ports, respectively,
wherein each memory is configured to store the sequence of states that succeeds as a reference sequence, respectively, and
wherein each of the first semiconductor device and the second semiconductor device changes at least one of the PHY parameters and determines whether link configuration is successful by comparing a sequence of states, executed by the LTSSM to configure a link, with the reference sequence.
20. The system of claim 19 , wherein:
the reference sequence, stored in the memory of the first semiconductor device, is different from the reference sequence stored in the memory of the second semiconductor device.