Granted Patent B2

US 12,347,355 · App. 18/553,544 · Granted Jul 1, 2025

Inventors: You Pan (Hubei, CN); Mang Zhao (Hubei, CN); Qiang Gong (Hubei, CN)

Assignee: WUHAN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.

G09G3/20G11C19/287G09G2310/0267G09G2310/0286G09G2330/04

Abstract

Claims (41)

1. A gate driving circuit, comprising a plurality of gate driving units cascaded in a multi-stage series, each stage gate driving units comprising: a pull-up control module;

a pull-up node; a pull-down control module; a pull-down node; and

a pull-down module, wherein the pull-up control module is electrically connected to the pull-up node and configured to pull up a potential of the pull-up node; the pull-down control module which disconnects to the pull-up node, is electrically connected to the pull-down node, and is configured to pull down a potential of the pull-down node; and the pull-down module is electrically connected to the pull-up node and the pull-down node, and is configured to pull down the potential of the pull-up node under control of the potential of the pull-down node,

wherein the pull-down module comprises a fifth transistor;

a gate of the fifth transistor is electrically connected to the pull-down node, a first electrode of the fifth transistor is electrically connected to a reference low-level signal input terminal, and a second electrode of the fifth transistor is electrically connected to the pull-up node,

wherein the pull-down module further comprises a sixth transistor;

a gate of the sixth transistor is electrically connected to a scanning signal input terminal of a next one stage gate driving unit, a first electrode of the sixth transistor is electrically connected to a reference low-level signal input terminal, and a second electrode of the sixth transistor is electrically connected to the pull-up node, and

wherein the sixth transistor is provided in all stage gate driving units except a last stage gate driving unit.

2. The gate driving circuit according to claim 1 , wherein the pull-up control module comprises a first transistor;

a gate of the first transistor is electrically connected to a scanning signal input terminal of a previous one stage gate driving unit, a first electrode of the first transistor is electrically connected to a reference high-level signal input terminal, and a second electrode of the first transistor is electrically connected to the pull-up node.

3. The gate driving circuit according to claim 1 , wherein the pull-down control module comprises a second transistor;

a gate of the second transistor is electrically connected to a scanning signal input terminal of a previous one stage gate driving unit or a scanning signal input terminal of a previous two stage gate driving unit, a first electrode of the second transistor is electrically connected to a reference low-level signal input terminal, and a second electrode of the second transistor is electrically connected to the pull-down node.

4. The gate driving circuit according to claim 1 , wherein the pull-down control module comprises a third transistor and a fourth transistor;

a first electrode of the third transistor is electrically connected to a reference low-level signal input terminal, a second electrode of the third transistor is electrically connected to the pull-down node;

a gate of the fourth transistor is electrically connected to a scanning signal input terminal of a previous one stage gate driving unit or a scanning signal input terminal of a previous two stage gate driving unit, a first electrode of the fourth transistor is electrically connected to a reference high-level signal input terminal, and a second electrode of the fourth transistor is electrically connected to a gate of the third transistor.

5. The gate driving circuit according to claim 1 , wherein the pull-down module further comprises a seventh transistor;

a gate of the seventh transistor is electrically connected to a clock signal input terminal of a next one stage gate driving unit, a first electrode of the seventh transistor is electrically connected to a reference low-level signal input terminal or an all-gate-on control signal input terminal, and a second electrode of the seventh transistor is electrically connected to the pull-up node.

6. The display panel according to claim 5 , wherein the seventh transistor is provided in a last stage gate driving unit.

7. The display panel according to claim 1 , wherein the gate driving unit further comprises an output control module and an output module;

the output control module is electrically connected to the pull-down node, and is configured to pull up a potential of the pull-down node;

the output module is electrically connected to the pull-up node, and is configured to output a scanning signal.

8. A display panel, comprising a pixel unit and a gate driving circuit,

wherein the gate driving circuit is electrically connected to the pixel unit and comprises a plurality of gate driving units cascaded in a multi-stage series, each stage gate driving units comprises: a pull-up control module; a pull-up node; a pull-down control module; a pull-down node; and a pull-down module, the pull-up control module is electrically connected to the pull-up node, and is configured to pull up a potential of the pull-up node; the pull-down control module which disconnect to the pull-up node, is electrically connected to the pull-down node, and is configured to pull down a potential of the pull-down node; and the pull-down module is electrically connected to the pull-up node and the pull-down node, and is configured to pull down the potential of the pull-up node under control of the potential of the pull-down node,

wherein the pull-down module includes a fifth transistor;

a gate of the fifth transistor is electrically connected to the pull-down node, a first electrode of the fifth transistor is electrically connected to a reference low-level signal input, and a second electrode of the fifth transistor is electrically connected to the pull-up node,

wherein the pull-down module further comprises a sixth transistor;

a gate of the sixth transistor is electrically connected to a scanning signal input terminal of a next one stage gate driving unit, a first electrode of the sixth transistor is electrically connected to a reference low-level signal input terminal, and a second electrode of the sixth transistor is electrically connected to the pull-up node, and

wherein the sixth transistor is provided in all stage gate driving units except a last stage gate driving unit.

9. The display panel according to claim 8 , wherein the pull-up control module comprises a first transistor;

a gate of the first transistor is electrically connected to a scanning signal input terminal of a previous one stage gate driving unit, a first electrode of the first transistor is electrically connected to a reference high-level signal input, and a second electrode of the first transistor is electrically connected to the pull-up node.

10. The display panel according to claim 8 , wherein the pull-down control module comprises a second transistor;

a gate of the second transistor is electrically connected to a scanning signal input terminal of a previous one stage gate driving unit or a scanning signal input terminal of a previous two stage gate driving unit, a first electrode of the second transistor is electrically connected to a reference low-level signal input terminal, and a second electrode of the second transistor is electrically connected to the pull-down node.

11. The display panel according to claim 8 , wherein the pull-down control module comprises:

a third transistor and a fourth transistor;

a first electrode of the third transistor is electrically connected to a reference low-level signal input terminal, a second electrode of the third transistor is electrically connected to the pull-down node; and

a gate of the fourth transistor is electrically connected to a scanning signal input terminal of a previous one stage gate driving unit or a scanning signal input terminal of a previous two stage gate driving unit, a first electrode of the fourth transistor is electrically connected to a reference high-level signal input terminal, and a second electrode of the fourth transistor is electrically connected to a gate of the third transistor.

12. The display panel according to claim 8 , wherein the pull-down module further comprises a seventh transistor; a gate of the seventh transistor is electrically connected to a clock signal input terminal of a next one stage gate driving unit, a first electrode of the seventh transistor is electrically connected to a reference low-level signal input terminal or an all-gate-on control signal input terminal, and a second electrode of the seventh transistor is electrically connected to the pull-up node.

13. The display panel according to claim 12 , wherein the seventh transistor is provided in a last stage gate driving unit.

14. The display panel according to claim 8 , wherein the gate driving unit further comprises an output control module and an output module;

the output control module is electrically connected to the pull-down node, and is configured to pull up a potential of the pull-down node; and

the output module is electrically connected to the pull-up node, and is configured to output a scanning signal.

Assignments (1)

Priority Claims (1)

Continuity (1)

References Cited (13)