Semiconductor memory device

1. A semiconductor memory device, comprising:

a first chip having a plurality of wiring layers stacked in a first direction, and a plurality of memory pillars extending into the plurality of wiring layers in the first direction;

a second chip having a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate, the second chip bonded to the first chip; and

a plurality of bonding pads provided at a bonding face between the first chip and the second chip, wherein

the plurality of bonding pads include:

a first bonding pad electrically connecting a first memory pillar among the plurality of memory pillars to one of the plurality of transistors, and

a second bonding pad adjacent the first bonding pad when seen from the first direction, the second bonding pad electrically connecting a second memory pillar among the plurality of memory pillars to one of the plurality of transistors, and

wherein the second memory pillar is not adjacent the first memory pillar when seen from the first direction.

2. The semiconductor memory device according to claim 1 , wherein

the first chip further includes a plurality of bit lines disposed below the plurality of memory pillars, the plurality of bit lines (i) extending in a second direction intersecting the first direction, and (ii) arranged in a third direction intersecting the first direction and the second direction,

the plurality of bit lines having (i) a first bit line connecting the first memory pillar to the first bonding pad and (ii) a second bit line connecting the second memory pillar to the second bonding pad, and

at least seven of the plurality of bit lines arranged between the first bit line and the second bit line in the third direction.

3. The semiconductor memory device according to claim 2 , wherein

the plurality of bonding pads are disposed sequentially in the third direction, and in a fourth direction opposite to the third direction, such that the at least seven bit lines are arranged between the bit lines to which the bonding pads are connected.

4. The semiconductor memory device according to claim 2 , wherein

multiple bonding pads are disposed sequentially in the third direction such that the at least seven bit lines are arranged between the bit lines to which the bonding pads are connected.

5. The semiconductor memory device according to claim 2 , wherein

each of the plurality of bonding pads is connected to a respective one of the plurality of bit lines via a first via plug, a wiring layer, and a second via plug, and

the second via plugs connected to the adjacent abonding pads are disposed in the wiring layer such that that the at least seven bit lines are arranged between the bit lines to which the second via plugs are connected.

6. The semiconductor memory device according to claim 1 , wherein

the first chip is an array chip including a memory cell array, and

the second chip is a circuit chip including a control circuit configured to control the array chip.

7. A semiconductor memory device, comprising:

a first chip having a plurality of wiring layers stacked in a first direction and a plurality of memory pillars penetrating the plurality of wiring layers in the first direction;

a second chip having a semiconductor substrate and a plurality of transistors provided on the semiconductor substrate, the second chip being bonded to the first chip; and

a plurality of bonding pads provided at a bonding face between the first chip and the second chip, wherein

the plurality of bonding pads include:

a first bonding pad electrically connecting a first memory pillar among the plurality of memory pillars to one of the plurality of transistors, and

a second bonding pad electrically connecting a second memory pillar among the plurality of memory pillars, the second bonding pad adjacent the first memory pillar when seen from the first direction, to one of the plurality of transistors, and

wherein the second bonding pad is not adjacent the first bonding pad when seen from the first direction.

8. The semiconductor memory device according to claim 6 , wherein the first chip includes an array region including the memory cell array, a stepped region, and a peripheral region.

9. The semiconductor memory device according to claim 8 , wherein the plurality of wiring layers are disposed in the stepped region.

10. The semiconductor memory device according to claim 1 , where each of the plurality of memory pillars includes a semiconductor pillar.

11. The semiconductor memory device according to claim 10 , where each of the plurality of memory pillars includes a charge storage layer.

12. The semiconductor memory device according to claim 1 , where the plurality of wiring layers include word lines.

13. The semiconductor memory device according to claim 7 , wherein

the first chip is an array chip including a memory cell array, and

the second chip is a circuit chip including a control circuit configured to control the array chip.

14. The semiconductor memory device according to claim 13 , wherein the first chip includes an array region including the memory cell array, a stepped region, and a peripheral region.

15. The semiconductor memory device according to claim 14 , wherein the plurality of wiring layers are disposed in the stepped region.

16. The semiconductor memory device according to claim 7 , where each of the plurality of memory pillars includes a semiconductor pillar.

17. The semiconductor memory device according to claim 16 , where each of the plurality of memory pillars includes a charge storage layer.

18. The semiconductor memory device according to claim 7 , where the plurality of wiring layers include word lines.