Semiconductor devices and methods of manufacturing thereof
View Patent ↗A method of fabricating a semiconductor device is described. A semiconductor substrate having at least one electrical component is provided. A patterned wiring layer is formed above the semiconductor substrate. The patterned wiring layer includes a plurality of wiring portions, where adjacent of the wiring portions are separated from each other. A first insulating passivation layer is formed over the wiring portions in a region between adjacent wiring portions. The first insulating passivation layer has a horizontal surface in the region between adjacent wiring portions. A second insulating passivation layer is formed on the first insulating passivation layer, wherein the first insulating passivation layer has a side surface which makes an angle with the horizontal surface of greater than 103°.
1. A method of fabricating a semiconductor device, comprising:
providing a semiconductor substrate having at least one electrical component;
forming a patterned wiring layer above the semiconductor substrate, the patterned wiring layer including a plurality of wiring portions, wherein sidewalls of adjacent wiring portions are separated from each other, the sidewalls making a first angle with a horizontal surface in a region between the adjacent wiring portions;
forming a first insulating passivation layer over the wiring portions in the region between the adjacent wiring portions, the first insulating passivation layer having the horizontal surface, wherein the first insulating passivation layer has a side surface which makes an angle with the horizontal surface of greater than:
the first angle; and
103°; and
forming a second insulating passivation layer on the first insulating passivation layer,
wherein the first insulating passivation layer and the second insulating passivation layer do not have a void in the region between adjacent wiring lines.
2. The method of fabricating a semiconductor device according to claim 1 , wherein the first insulating passivation layer includes SiOx and is formed using an undoped silicate glass (USG) or a high density plasma (HDP) deposition technique.
3. The method of fabricating a semiconductor device according to claim 1 , wherein the first insulating passivation layer includes SiOx and is formed using a high density plasma (HDP) deposition technique wherein the SiOx first insulating passivation layer has a deposition rate and a sputtering rate, wherein a ratio of the deposition rate to the sputtering rate is 2-4.
4. The method of fabricating a semiconductor device according to claim 1 , wherein the second insulating passivation layer includes SiOx and is formed using a plasma enhanced tetraethyl orthosilicate (PETEOS) deposition technique.
5. The method of fabricating a semiconductor device according to claim 1 , further comprising forming a third insulating passivation layer on the second insulating passivation layer.
6. The method of fabricating a semiconductor device according to claim 5 , wherein the third insulating passivation layer includes SiN and is formed using a plasma enhanced deposition method.
7. The method of fabricating a semiconductor device according to claim 1 , wherein the second insulating passivation layer has compressive stress.
8. The method of fabricating a semiconductor device according to claim 7 , wherein the wiring portions have a tensile stress.
9. The method of fabricating a semiconductor device according to claim 7 , further comprising forming a third insulating passivation layer on the second insulating passivation layer.
10. A method of fabricating a semiconductor device, comprising:
providing a semiconductor substrate having at least one electrical component;
forming a patterned wiring layer above the semiconductor substrate, the patterned wiring layer including a plurality of wiring portions in which sidewalls of adjacent wiring portions are separated from each other, the sidewalls making a first angle with a horizontal surface in a region between the adjacent wiring portions;
forming a first insulating passivation layer having a first compressive stress over the wiring portions in the region between the adjacent wiring portions, the first insulating passivation layer having the horizontal surface, wherein the first insulating passivation layer has a side surface which makes an angle with the horizontal surface of greater than the first angle and 103°; and
forming a second insulating passivation layer on the first insulating passivation layer, wherein the second insulating passivation layer has a second compressive stress greater than the first compressive stress, the first compressive stress exceeding a third compressive stress of a layer disposed over the second insulating layer.
11. The method of fabricating a semiconductor device according to claim 10 , wherein the wiring portions have a tensile stress.
12. The method of fabricating a semiconductor device according to claim 10 , further comprising forming a third insulating passivation layer on the second insulating passivation layer.
13. The method of fabricating a semiconductor device according to claim 10 , wherein the first insulating passivation layer includes SiOx and is formed using an undoped silicate glass (USG) or a high density plasma (HDP) deposition technique.
14. The method of fabricating a semiconductor device according to claim1 10 , wherein the first insulating passivation layer includes SiOx and is formed using a high density plasma (HDP) deposition technique wherein the SiOx first insulating passivation layer has a deposition rate and a sputtering rate, wherein a ratio of the deposition rate to the sputtering rate is 2-4.
15. The method of fabricating a semiconductor device according to claim 10 , wherein the second insulating passivation layer includes SiOx and is formed using a plasma enhanced tetraethyl orthosilicate (PETEOS) deposition technique.
16. The method of fabricating a semiconductor device according to claim 10 , further comprising forming a third insulating passivation layer on the second insulating passivation layer.
17. The method of fabricating a semiconductor device according to claim 16 , wherein the third insulating passivation layer includes SiN and is formed using a plasma enhanced deposition method.
18. A method of fabricating a semiconductor device, comprising:
providing a semiconductor substrate having at least one electrical component;
forming a patterned wiring layer above the semiconductor substrate, the patterned wiring layer including a plurality of wiring portions in which sidewalls of adjacent wiring portions are separated from each other, the sidewalls making a first angle with a horizontal surface in a region between the adjacent wiring portions;
forming a first insulating passivation layer having a first compressive stress over the wiring portions in the region between the adjacent wiring portions, the first insulating passivation layer having the horizontal surface, wherein the first insulating passivation layer has a side surface which makes an angle with the horizontal surface of greater than the first angle and 103°; and
forming a second insulating passivation layer on the first insulating passivation layer.
19. The method of claim 18 , wherein the first insulating passivation layer includes SiOx and is formed using an undoped silicate glass (USG) or a high density plasma (HDP) deposition technique.
20. The method of claim 18 , wherein the first insulating passivation layer includes SiOx and is formed using a high density plasma (HDP) deposition technique wherein the SiOx first insulating passivation layer has a deposition rate and a sputtering rate, wherein a ratio of the deposition rate to the sputtering rate is 2-4.
21. The method of claim 18 , wherein the second insulating passivation layer includes SiOx and is formed using a plasma enhanced tetraethyl orthosilicate (PETEOS) deposition technique.