IP Library › Granted Patent US 12,348,235
Granted Patent B2
US 12,348,235 · App. 18/181,477 · Granted Jul 1, 2025

Supply voltage based or temperature based fine control of a tunable oscillator of a PLL

Inventors: Siddhartha Hazra (West Bengal, IN); Hormoz Djahanshahi (Port Moody, CA)
Assignee: Microchip Technology Incorporated
H03L7/0991H03L1/00H03L1/026
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Quick Facts
Patent No.
US 12,348,235
App. No.
18/181,477
Granted
Jul 1, 2025
Kind
B2
Abstract

One or more examples relate, generally to supply voltage based or temperature based fine control of a tunable oscillator of a PLL. An associated method includes: receiving one or more values indicative of temperature or supply voltage of a phase-locked loop (PLL); setting a digital fine-tuning control code to an initialization code, the initialization code at least partially based on the received one or more values indicative of temperature or supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of a tunable oscillator; and starting, with the set digital fine-tuning control code, a process to set an initial frequency of the oscillator at or close to a target frequency. The process may be a calibration process performed before initially acquiring lock or re-acquiring lock.

Claims (76)

1. A method, comprising:

receiving values indicative of temperature of a tunable oscillator and supply voltage of a phase-locked loop (PLL);

setting a digital fine-tuning control code based on an initialization code, the initialization code at least partially based on the received values indicative of one or more of a temperature value of the tunable oscillator and a supply voltage value of the PLL, wherein the digital fine-tuning control code is to set a number of tuning-elements within a fine bank of the tunable oscillator; and

starting a calibration of the PLL with the set digital fine-tuning control code, the calibration to set an initial frequency of the tunable oscillator at or close to a target frequency, wherein the PLL includes a digital integral control path and proportional control paths.

2. The method of claim 1 , wherein setting the digital fine-tuning control code to the initialization code comprises:

obtaining an offset code associated with the received values indicative of one or more of a temperature value of the tunable oscillator and supply voltage of the PLL;

setting the initialization code to one-half (½) range of the digital fine-tuning control code; and

changing the set initialization code by an amount represented by the offset code.

3. The method of claim 2 , wherein setting the digital fine-tuning control code to the initialization code comprises:

setting the digital fine-tuning control code to the changed set initialization code.

4. The method of claim 1 , comprising:

obtaining parameters representing a frequency response of the tunable oscillator to changes in supply voltage and temperature, and predetermined ranges of temperature and supply voltage;

determining a number of tuning-elements within a fine-tuning bank of a tunable oscillator;

determining respective frequencies of the tunable oscillator in response to respective temperature values and respective supply voltage values, and determining respective offset codes to compensate for the determined frequencies utilizing the tuning-elements within the fine-tuning bank of the tunable oscillator; and

storing the determined offset codes in a look-up table or utilizing a determined offset code to determine the initialization code.

5. The method of claim 1 , comprising:

performing a coarse calibration process starting with the set digital-fine tuning control code;

setting a coarse-tuning control code at least partially responsive to the coarse calibration process;

performing a fine calibration process after the coarse calibration process; and

setting the fine-tuning control code at least partially responsive to the fine calibration process.

6. The method of claim 1 , comprising:

obtaining an integral control code;

detecting post-calibration temperature drift, supply voltage drift, or combination thereof, at least partially responsive to the integral control code; and

set a drift control code to a value proportional to post-calibration drift indicated by the integral control code.

7. The method of claim 6 , comprising:

change a control code applied to an input of the fine bank of tuning-elements in an amount proportional to the set drift control code.

8. The method of claim 6 , wherein the detecting post-calibration drift comprises:

comparing the integral control code with a first predetermined threshold value;

detecting a first state of the tunable oscillator if the integral control code is higher than the first predetermined value, wherein the first state corresponds to unacceptable post-calibration drift toward a lower output frequency;

comparing the integral control code with a second predetermined threshold value;

detecting a second state of the tunable oscillator if the integral control code is lower than the second predetermined threshold value, wherein the second state corresponds to unacceptable post-calibration drift toward a higher output frequency; and

detecting a third state of the tunable oscillator if the integral control code is lower than the first threshold predetermined value and higher than the second threshold predetermined value, wherein the third state corresponds to no or acceptable post-calibration drift.

9. The method of claim 1 , wherein the PLL includes a digital integral control path and an analog proportional control path.

10. The method of claim 1 , wherein the proportional control paths include a digital proportional control path.

11. An apparatus, comprising:

a processor; and

a data storage device to store machine-executable code including executable instructions to adapt or enable the processor to:

receive values indicative of temperature of a tunable oscillator and supply voltage of a phase-locked loop (PLL);

set a digital fine-tuning control code based on an initialization code, the initialization code at least partially based on the received values indicative of one or more of a temperature value of the tunable oscillator and a supply voltage of the PLL, wherein the digital fine-tuning control code for setting a number of tuning-elements within a fine bank of the tunable oscillator; and

start calibration of the PLL with the set digital fine-tuning control code, wherein the executable instructions to adapt or enable the processor to set the digital fine-tuning control code to the initialization code to:

obtain an offset code associated with the received values indicative of one or more of a temperature value of the tunable oscillator and supply voltage of the PLL;

set the initialization code to one-half (½) range of the digital fine-tuning control code; and

change the set initialization code by an amount represented by the offset code.

12. The apparatus of claim 11 , wherein the executable instructions to adapt or enable the processor to set the digital fine-tuning control code to the initialization code comprise executable instructions to:

set the digital fine-tuning control code to the changed set initialization code.

13. The apparatus of claim 11 , wherein the machine-executable code including executable instructions to adapt or enable the processor to:

obtain parameters representing a frequency response of the tunable oscillator to changes in supply voltage and temperature, and predetermined ranges of temperature and supply voltage;

determine a number of tuning-elements within a fine-tuning bank of a tunable oscillator;

determine respective frequencies of the tunable oscillator in response to respective temperature values and respective supply voltage values, and determine respective offset codes to compensate for the determined frequencies utilizing the tuning-elements within the fine-tuning bank of the tunable oscillator; and

store the determined offset codes in a look-up table or utilizing the determined offset codes to determine the initialization code.

14. The apparatus of claim 11 , wherein the machine-executable code including executable instructions to adapt or enable the processor to:

perform a coarse calibration process starting with the set digital-fine tuning control code;

set a coarse-tuning control code at least partially responsive to the coarse calibration process;

perform a fine calibration process after the coarse calibration process; and

set the fine-tuning control code at least partially responsive to the fine calibration process.

15. The apparatus of claim 11 , wherein the machine-executable code including executable instructions to adapt or enable the processor to:

obtain an integral control code;

detect post-calibration drift at least partially responsive to changes in the integral control code; and

set a drift control code to a value proportional to post-calibration drift indicated by changes in the integral control code.

16. The apparatus of claim 15 , wherein the machine-executable code including executable instructions to adapt or enable the processor to:

changing the fine-tuning control code having been set responsive to a fine calibration process in an amount proportional to the set drift control code.

17. An apparatus comprising:

a tunable oscillator to generate an output signal;

an error detector to generate an error signal indicative of a phase or frequency difference between the output signal and a reference signal;

a voltage monitor to generate a value representative of a supply voltage of the apparatus;

a temperature monitor to generate a value representative of the temperature of the apparatus;

one or more controllers to provide to the tunable oscillator:

a proportional control signal to the tunable oscillator least partially responsive to the error signal generated by the error detector;

an integral control code or an integral control signal;

a coarse-tuning control code; and

a fine-tuning control code, wherein the one or more controller to set the fine-tuning control code at least partially responsive to one or more of the values respectively representative of the supply voltage of the apparatus or the temperature of the apparatus.

18. The apparatus of claim 17 , wherein the integral control code or the integral control signal is indicative of magnitude of integral control action applied to the tunable oscillator to urge the oscillator frequency toward a target frequency.

19. The apparatus of claim 17 , comprising:

an analog controller of the one or more controllers, the analog controller to provide the proportional control signal; and

a digital controller of the one or more controllers, the digital controller to provide the integral control code or an integral control signal, the coarse-tuning control code, and the fine-tuning control code.

20. The apparatus of claim 17 , comprising a digital controller of the one or more controllers, the digital controller to provide: the proportional control signal, the integral control code or an integral control signal, the coarse-tuning control code, and the fine-tuning control code.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 10, 2023
From: HAZRA, SIDDHARTHA; DJAHANSHAHI, HORMOZ
To: MICROCHIP TECHNOLOGY INCORORATED
Reel/Frame 062943/0489 →
Priority Claims (1)
IN 202241012666 · Mar 9, 2022 · national
Continuity (1)
Related Publication 20230291408A1 · Sep 14, 2023
References Cited (16)
US 5204975A · Shigemori · 1993 [cited by applicant]
US 9742354B2 · Djahanshahi et al. · 2017 [cited by applicant]
US 9787251B2 · Djahanshahi et al. · 2017 [cited by applicant]
US 10187071B2 · Arora et al. · 2019 [cited by applicant]
US 10389301B2 · Djahanshahi et al. · 2019 [cited by applicant]
US 10749470B2 · Djahanshahi et al. · 2020 [cited by applicant]
US 20020075080A1 · Nelson et al. · 2002 [cited by applicant]
US 20080002801A1 · Droege · 2008 [cited by examiner]
US 20080129398A1 · Sun · 2008 [cited by examiner]
US 20170093409A1 · Djahanshahi et al. · 2017 [cited by applicant]
US 20190036537A1 · Dorner · 2019 [cited by examiner]
EP 3340467A1 · 2018 [cited by applicant]
WO 2010104891A1 · 2010 [cited by applicant]
International Search Report for International Application No. PCT/US2023/064072, mailed Jul. 12, 2023, 6 pages. [cited by applicant]
Written Opinion of the International Searching Authority of International Application No. PCT/US2023/064072, mailed Jul. 12, 2023, 8 pages. [cited by applicant]
Djahanshahi, Hormoz, et al., Method and Apparatus for Reconfigurable Multicore Oscillator, filed Oct. 4, 2016, U.S. Appl. No. 62/403,939, 52 pages. [cited by applicant]