2D channel with self-aligned source/drain

1. A method, comprising:

forming a channel region of a transistor in an integrated circuit;

forming a first source or drain region of the transistor in contact with a first lateral end of the channel region;

forming a second source or drain region of the transistor in contact with a second lateral end of the channel region;

forming a gate dielectric of the transistor in contact with the channel region and aligned with the first and second lateral ends of the channel region; and

forming a gate metal in contact with the gate dielectric, wherein the channel region is vertically between the gate metal and the first source or drain region.

2. The method of claim 1 , further comprising flipping the integrated circuit between forming the first source or drain region and forming the gate metal.

3. The method of claim 1 , further comprising:

forming the channel region by depositing the channel region on a substrate;

forming a first trench and a second trench in the channel region and the substrate;

forming a dielectric layer in the first and second trenches; and

forming the first source or drain region in the first trench on the dielectric layer and in contact with the channel region and a second source or drain region in the second trench on the dielectric layer and in contact with the channel region by depositing a metal in the first and second trenches.

4. The method of claim 3 , comprising:

flipping the integrated circuit after forming the first and second source or drain regions;

removing the substrate after flipping the integrated circuit;

forming the gate dielectric by depositing the gate dielectric on the channel region and the dielectric layer after removing the substrate; and

forming the gate metal by depositing the gate metal on the gate dielectric.

5. The method of claim 1 , wherein the gate metal laterally overlaps the first and second source or drain regions by a substantially equal amount.

6. The method of claim 1 , wherein the gate metal laterally overlaps the first source or drain region by a larger amount than the second source or drain region.

7. A method, comprising:

depositing a channel region of a transistor in an integrated circuit;

patterning the channel region;

forming first and second source or drain regions of the transistor in contact with lateral ends of the channel region;

flipping the integrated circuit;

depositing a gate dielectric in contact with the channel region and the first and second source or drain regions after flipping the integrated circuit; and

depositing a gate metal in contact with the gate dielectric.

8. The method of claim 7 , wherein the channel region is a two dimensional channel region.

9. The method of claim 7 , wherein the channel region includes carbon nanotubes.

10. A method, comprising:

forming a first source or drain region of a transistor;

forming a second source or drain region of the transistor;

forming a two dimensional channel region of the transistor extending between the first source or drain region and the second source or drain region and having a first lateral end on the first source or drain region and a second lateral end on the second source or drain region;

forming a gate dielectric on the channel region and having a lateral surface that is substantially coplanar with the first lateral end of the channel region; and

forming a gate metal on the gate dielectric and laterally bounded by the gate dielectric, wherein the gate metal vertically overlaps the first second source or drain region and the second source or drain region.

11. The method of claim 10 , wherein the gate metal laterally overlaps the first and second source or drain regions by a substantially equal amount.

12. The method of claim 10 , wherein the gate metal laterally overlaps the first and second source or drain regions by between 1 nm and 30 nm.

13. The method of claim 10 , wherein the gate metal laterally overlaps the first source or drain region by a larger amount than the second source or drain region.

14. The method of claim 13 , wherein the gate metal laterally overlaps the first source or drain region by between 1 nm and 30 nm, wherein the gate metal laterally overlaps the second source or drain region by less than 25 nm.

15. The method of claim 13 , wherein the first source or drain region is a source region, wherein the second source or drain region is a drain region.

16. The method of claim 10 , wherein:

the first source or drain region has a first step structure including a horizontal surface and a vertical surface;

the channel region is positioned on the horizontal surface of the first step structure; and

the first lateral end of the channel region abuts the vertical surface of the first step structure.

17. The method of claim 16 , wherein the gate dielectric abuts the vertical surface of the first step structure.

18. The method of claim 16 , wherein:

the second source or drain region has a second step structure including a horizontal surface and a vertical surface;

the channel region is positioned on the horizontal surface of the second step structure; and

the second lateral end of the channel region abuts the vertical surface of the second step structure.

19. The method of claim 10 , wherein the channel region is positioned vertically between the gate metal and the first source or drain region.

20. The method of claim 10 , further comprising:

forming a first conductive via below and in contact with the first source or drain region; and

forming a second conductive via above and in contact with the gate metal.