Trench plug hardmask for advanced integrated circuit structure fabrication
Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin comprising silicon. A plurality of gate structures is over the fin, individual ones of the plurality of gate structures along a direction orthogonal to the fin and having a pair of dielectric sidewall spacers. A trench contact structure is over the fin and directly between the dielectric sidewalls spacers of a first pair of the plurality of gate structures. A contact plug is over the fin and directly between the dielectric sidewalls spacers of a second pair of the plurality of gate structures, the contact plug comprising a lower dielectric material and an upper hardmask material.
1. An integrated circuit structure, comprising:
a fin comprising silicon;
a gate structure over the fin, the gate structure along a direction orthogonal to the fin;
a first dielectric sidewall spacer adjacent to a first side of the gate structure;
a second dielectric sidewall spacer adjacent to a second side of the gate structure;
a trench contact structure over the fin and adjacent to the first dielectric sidewall spacer; and
a contact plug over the fin and adjacent to the second dielectric sidewall spacer, the contact plug comprising a lower dielectric material and an upper hardmask material, the upper hardmask material having a rounded bottom surface.
2. The integrated circuit structure of claim 1 , wherein the lower dielectric material of the contact plug comprises silicon and oxygen, and the upper hardmask material of the contact plug comprises silicon and nitrogen.
3. The integrated circuit structure of claim 1 , wherein the trench contact structure comprises a lower conductive structure and a dielectric cap on the lower conductive structure.
4. The integrated circuit structure of claim 3 , wherein the dielectric cap of the trench contact structure has an upper surface co-planar with an upper surface of the upper hardmask material of the contact plug.
5. The integrated circuit structure of claim 1 , wherein the gate structure comprises a gate electrode on a gate dielectric layer, and a dielectric cap on the gate electrode.
6. The integrated circuit structure of claim 5 , wherein the dielectric cap of the gate structure has an upper surface co-planar with an upper surface of the upper hardmask material of the contact plug.
7. The integrated circuit structure of claim 1 , wherein the fin is continuous with a bulk crystalline silicon substrate.
8. An integrated circuit structure, comprising:
a nanowire comprising silicon;
a gate structure over the nanowire and completely surrounding a channel region of the nanowire;
a first dielectric sidewall spacer adjacent to a first side of the gate structure;
a second dielectric sidewall spacer adjacent to a second side of the gate structure;
a trench contact structure above the nanowire and adjacent to the first dielectric sidewall spacer; and
a contact plug above the nanowire and adjacent to the second dielectric sidewall spacer, the contact plug comprising a lower dielectric material and an upper hardmask material, the upper hardmask material having a rounded bottom surface.
9. The integrated circuit structure of claim 8 , wherein the lower dielectric material of the contact plug comprises silicon and oxygen, and the upper hardmask material of the contact plug comprises silicon and nitrogen.
10. The integrated circuit structure of claim 8 , wherein the trench contact structure comprises a lower conductive structure and a dielectric cap on the lower conductive structure.
11. The integrated circuit structure of claim 10 , wherein the dielectric cap of the trench contact structure has an upper surface co-planar with an upper surface of the upper hardmask material of the contact plug.
12. The integrated circuit structure of claim 8 , wherein the gate structure comprises a gate electrode on a gate dielectric layer, and a dielectric cap on the gate electrode.
13. The integrated circuit structure of claim 12 , wherein the dielectric cap of the gate structure has an upper surface co-planar with an upper surface of the upper hardmask material of the contact plug.
14. A system, comprising:
a board; and
a component coupled to the board, the component comprising an integrated circuit structure, the integrated circuit structure comprising:
a fin comprising silicon;
a gate structure over the fin, the gate structure along a direction orthogonal to the fin;
a first dielectric sidewall spacer adjacent to a first side of the gate structure;
a second dielectric sidewall spacer adjacent to a second side of the gate structure;
a trench contact structure over the fin and adjacent to the first dielectric sidewall spacer; and
a contact plug over the fin and adjacent to the second dielectric sidewall spacer, the contact plug comprising a lower dielectric material and an upper hardmask material, the upper hardmask material having a rounded bottom surface.
15. The system of claim 14 , further comprising:
a memory coupled to the board.
16. The system of claim 14 , further comprising:
a communication chip coupled to the board.
17. The system of claim 14 , further comprising:
a battery coupled to the board.
18. The system of claim 14 , further comprising:
a camera coupled to the board.
19. The system of claim 14 , further comprising:
a GPS coupled to the board.
20. The system of claim 14 , further comprising:
a display coupled to the board.