High-voltage semiconductor device structures
Device structures for a high-voltage semiconductor device and methods of forming such device structures. The structure comprises a semiconductor substrate including a trench, and a field-effect transistor including a first and second source/drain regions in the semiconductor substrate, a gate dielectric inside the trench, and a gate on the gate dielectric. The gate and the gate dielectric are disposed laterally between the first and second source/drain regions.
1. A structure comprising:
a semiconductor substrate including a trench and a top surface; and
a first field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, a gate dielectric inside the trench, and a first gate on the gate dielectric, the first gate and the gate dielectric laterally positioned between the first source/drain region and the second source/drain region, the first source/drain region and the second source/drain region coextensive with the top surface of the semiconductor substrate, the gate dielectric including a first dielectric layer, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, the first dielectric layer and the second dielectric layer comprising silicon dioxide, the third dielectric layer comprising a high-k dielectric material, and the second dielectric layer coplanar with the top surface of the semiconductor substrate.
2. The structure of claim 1 wherein the first dielectric layer has a first thickness, and the second dielectric layer has a second thickness that is less than the first thickness.
3. The structure of claim 1 wherein the first dielectric layer of the gate dielectric extends to a first maximum depth relative to the top surface of the semiconductor substrate, the first source/drain region and the second source/drain region extend to a second maximum depth relative to the top surface of the semiconductor substrate, and the first maximum depth is greater than the second maximum depth.
4. The structure of claim 1 wherein the trench extends from the top surface of the semiconductor substrate into the semiconductor substrate, and the first dielectric layer has a top surface that is recessed below the top surface of the semiconductor substrate.
5. The structure of claim 4 wherein the first dielectric layer extends to a first maximum depth relative to the top surface of the semiconductor substrate, the first source/drain region and the second source/drain region extend to a second maximum depth relative to the top surface of the semiconductor substrate, and the first maximum depth is greater than the second maximum depth.
6. The structure of claim 1 wherein the first field-effect transistor is positioned in a first device region of the semiconductor substrate, and further comprising:
a second field-effect transistor in a second device region of the semiconductor substrate, the second field-effect transistor different from the first field-effect transistor.
7. The structure of claim 6 wherein the second field-effect transistor includes a semiconductor fin on the semiconductor substrate and a second gate extending transversely over the semiconductor fin.
8. The structure of claim 7 wherein the first gate has a first top surface, and the second gate has a second top surface that is substantially coplanar with the first top surface.
9. The structure of claim 7 the first gate has a first width, the second gate has a second width, and the first width is greater than the second width.
10. The structure of claim 7 wherein the first gate has a first thickness, the second gate has a second thickness, and the first thickness is equal to the second thickness.
11. The structure of claim 7 wherein the first gate and the second gate comprise a work function metal.
12. The structure of claim 1 further comprising:
a well in the semiconductor substrate;
a first doped region in a first portion of the well; and
a second doped region in a second portion of the well,
wherein the first doped region and the second doped region have an opposite conductivity type from the well, and the first source/drain region and the second source/drain region extend to a shallower depth in the semiconductor substrate than the first doped region and the second doped region.
13. The structure of claim 12 wherein the first doped region and the second doped region extend to a shallower depth in the semiconductor substrate than the well.
14. The structure of claim 13 wherein the first dielectric layer extends to a first maximum depth in the semiconductor substrate, and further comprising:
a trench isolation region that extends to a second maximum depth that is greater than the first maximum depth of the first dielectric layer.
15. The structure of claim 14 wherein the first source/drain region and the second source/drain region extend to a shallower depth in the semiconductor substrate than the first doped region and the second doped region.
16. A method comprising:
forming a trench in a semiconductor substrate; and
forming a field-effect transistor including a first source/drain region in the semiconductor substrate, a second source/drain region in the semiconductor substrate, a gate dielectric inside the trench, and a gate on the gate dielectric,
wherein the gate and the gate dielectric are laterally positioned between the first source/drain region and the second source/drain region, the semiconductor substrate has a top surface, the first source/drain region and the second source/drain region are coextensive with the top surface of the semiconductor substrate, the gate dielectric includes a first dielectric layer, a second dielectric layer on the first dielectric layer, and a third dielectric layer on the second dielectric layer, the first dielectric layer and the second dielectric layer comprise silicon dioxide, the third dielectric layer comprises a high-k dielectric material, and the second dielectric layer is coplanar with the top surface of the semiconductor substrate.