Granted Patent B2

US 12,349,601 · App. 17/832,883 · Granted Jul 1, 2025

Inventors: Xiaoguang Wang (Hefei, CN); Huihui Li (Hefei, CN); Xianqin Hu (Hefei, CN)

Assignees: CHANGXIN MEMORY TECHNOLOGIES, INC.; BEIJING SUPERSTRING ACADEMY OF MEMORY TECHNOLOGY

H10N50/80H10B61/00H10N50/01

Abstract

Claims (34)

1. A method for manufacturing a semiconductor structure, comprising:

providing a Magnetic Random Access Memory (MRAM) cell and an insulating layer, wherein the MRAM cell comprises a bottom electrode, a Magnetic Tunnel Junction (MTJ) stack, and a top electrode, and the insulating layer covers a top surface and a sidewall of the MRAM cell;

sequentially forming and stacking a first dielectric layer, a stop layer, and a second dielectric layer on the insulating layer;

performing a first etching on the second dielectric layer to form a first portion of a top electrode contact hole penetrating through the second dielectric layer and extending to the stop layer; and

performing a second etching on the first dielectric layer and the insulating layer to form a second portion of the top electrode contact hole penetrating through the first dielectric layer and the insulating layer, extending to the top electrode, and deepening the first portion, wherein a radial width of the second portion is gradually decreased with an increase in a depth of the top electrode contact hole;

wherein said forming the first dielectric layer or the second dielectric layer comprises: forming, by using a deposition parameter having a gradient change over time, the first dielectric layer or the second dielectric layer with a characteristic parameter having a gradient change along a depth direction of the top electrode contact hole; or

said performing the second etching on the first dielectric layer and the insulating layer comprises: performing the second etching on the first dielectric layer and the insulating layer by using an etching parameter having a gradient change over time.

2. The method of claim 1 , wherein a radial width of the first portion is greater than a radial width of the top electrode.

3. The method of claim 1 , wherein

said forming the first dielectric layer or the second dielectric layer comprises: forming, by using a deposition parameter having a gradient change over time, the first dielectric layer or the second dielectric layer with a characteristic parameter having a gradient change along a depth direction of the top electrode contact hole; and

said performing the second etching on the first dielectric layer and the insulating layer comprises: performing the second etching on the first dielectric layer and the insulating layer by using an etching parameter having a gradient change over time.

4. The method of claim 1 , wherein a radial width of the first portion is gradually decreased with the increase in the depth of the top electrode contact hole; and

said performing the first etching on the second dielectric layer comprises: performing the first etching on the second dielectric layer by using an etching parameter having a gradient change over time.

5. The method of claim 3 , wherein said forming the first dielectric layer or the second dielectric layer comprises:

forming a first consecutive dielectric layer or a second consecutive dielectric layer, wherein a characteristic parameter of the first consecutive dielectric layer or the second consecutive dielectric layer has a gradient change along the depth direction of the top electrode contact hole;

or,

forming the first dielectric layer or the second dielectric layer having a plurality of stacked sub-dielectric layers, wherein a characteristic parameter of the plurality of stacked sub-dielectric layers has a gradient change along the depth direction of the top electrode contact hole.

6. The method of claim 3 , wherein the deposition parameter at comprises at least one of:

a proportion of a chemical component of a reaction gas;

pressure;

temperature; or

power.

7. The method of claim 3 , wherein the characteristic parameter comprises at least one of

a proportion of a chemical component of the first dielectric layer or the second dielectric layer;

stress; or

rigidity.

8. The method of claim 3 , wherein an etch selectivity ratio of the first dielectric layer has a gradient change along the depth direction of the top electrode contact hole, and the etching parameter comprises at least one of:

a proportion of a chemical component of an etching gas;

temperature;

pressure; or

power.

9. The method of claim 1 , further comprising:

filling the top electrode contact hole with a conductive material; and

performing a planarization processing on the conductive material to form a top electrode contact plug.

Assignments (1)

Priority Claims (1)

Continuity (2)

References Cited (44)