Granted Patent B2

US 12,353,123 · App. 17/750,408 · Granted Jul 8, 2025

Inventors: Kazuhiro Segawa (Taichung, TW); Isao Tanaka (Taichung, TW)

Assignee: Winbond Electronics Corp.

G03F1/42G03F1/36

Abstract

Claims (29)

1. A semiconductor manufacturing apparatus, comprising:

a lithography apparatus;

a measurement apparatus measuring alignment mark position errors of a plurality of wafers; and

a processor coupled to the lithography apparatus and the measurement apparatus, grouping the wafers into a first wafer group and a second wafer group according to the alignment mark position errors of the wafers and a first threshold value, calculating a feedforward position correction value according to a difference between the alignment mark position errors of the first wafer group and a reference error value, and controlling the lithography apparatus to perform a lithography process according to the feedforward position correction value, wherein the alignment mark position errors of the first wafer group are greater than the first threshold value, and the alignment mark position errors of the second wafer group are less than or equal to the first threshold value.

2. The semiconductor manufacturing apparatus according to claim 1 , wherein the processor calculates the reference error value according to the alignment mark position errors of the second wafer group.

3. The semiconductor manufacturing apparatus according to claim 2 , wherein when the alignment mark position errors of the second wafer group are greater than a second threshold value, the processor corrects the feedforward position correction value according to the alignment mark position errors of the second wafer group.

4. The semiconductor manufacturing apparatus according to claim 1 , wherein the reference error value is obtained according to historical alignment mark position errors of the wafers with the alignment mark position errors less than or equal to the first threshold value in the previous lot of wafers.

5. The semiconductor manufacturing apparatus according to claim 1 , further comprising:

an overlay measurement apparatus coupled to the processor, wherein the overlay measurement apparatus measures overlay errors of the wafers, and the processor calculates an optimized position correction value according to the overlay errors of the wafers, the feedforward position correction value, and a position correction value used by the lithography apparatus when performing the lithography process on the previous wafer, and controls the lithography apparatus to perform the lithography process according to the optimized position correction value.

6. The semiconductor manufacturing apparatus according to claim 1 , further comprising:

an overlay measurement apparatus coupled to the processor, wherein the overlay measurement apparatus measures overlay errors of the wafers, and the processor calculates an optimized position correction value according to the overlay errors of the wafers and a position correction value used by the lithography apparatus when performing the lithography process on the previous wafer, and controls the lithography apparatus to perform the lithography process according to the optimized position correction value.

7. A semiconductor manufacturing method of a semiconductor manufacturing apparatus, comprising:

measuring alignment mark position errors of a plurality of wafers;

grouping the wafers into a first wafer group and a second wafer group according to the alignment mark position errors of the wafers and a first threshold value, wherein the alignment mark position errors of the first wafer group are greater than the first threshold value, and the alignment mark position errors of the second wafer group are less than or equal to the first threshold value;

calculating a feedforward position correction value according to a difference between the alignment mark position errors of the first wafer group and a reference error value; and

performing a lithography process according to the feedforward position correction value.

8. The semiconductor manufacturing method of the semiconductor manufacturing apparatus according to claim 7 , comprising:

calculating the reference error value according to the alignment mark position errors of the second wafer group.

9. The semiconductor manufacturing method of the semiconductor manufacturing apparatus according to claim 8 , comprising:

correcting the feedforward position correction value according to the alignment mark position errors of the second wafer group when the alignment mark position errors of the second wafer group are greater than a second threshold value.

10. The semiconductor manufacturing method of the semiconductor manufacturing apparatus according to claim 7 , wherein the reference error value is obtained according to historical alignment mark position errors of the wafers with the alignment mark position errors less than or equal to the first threshold value in the previous lot of wafers.

11. The semiconductor manufacturing method of the semiconductor manufacturing apparatus according to claim 7 , comprising:

measuring overlay errors of the wafers;

calculating an optimized position correction value according to the overlay errors of the wafers, the feedforward position correction value, and a position correction value used when performing the lithography process on the previous wafer; and

performing the lithography process according to the optimized position correction value.

12. The semiconductor manufacturing method of the semiconductor manufacturing apparatus according to claim 7 , comprising:

measuring overlay errors of the wafers;

calculating an optimized position correction value according to the overlay errors of the wafers and a position correction value used when performing the lithography process on the previous wafer; and

performing the lithography process according to the optimized position correction value.

Assignments (1)

Continuity (1)

References Cited (13)