Address embedding for encoder and decoder and data processing method thereof
A scheme for encoding and decoding a codeword into which address information is embedded. A write operation for this scheme includes generating tagging information including address information; encoding user information, meta information, the tagging information and additional shortened bits to generate parity information; generating a codeword including the user information, the meta information and the parity information; and storing the codeword in a memory device.
1. A method of operating a memory system including a memory device, the method comprising:
performing write and read operations,
wherein the write operation includes,
generating tagging information including address information and shortened bits added to the address information;
encoding a) user information, b) meta information, and c) the tagging information including the shortened bits added to the address information to generate parity information;
generating a codeword including the user information, the meta information and the parity information; and
storing the codeword in the memory device,
wherein the read operation includes,
reading the codeword read from the memory device;
adding, to the read codeword, tagging information including firmware (FW) address information in firmware to generate a modified codeword;
decoding, by a decoder, the modified codeword;
determining whether the decoding is successful based on decoding status;
determining an address mismatch when the firmware address information has been changed by the decoder; and
reporting the address mismatch to the firmware.
2. The method of claim 1 , wherein the address information is appended to the codeword and includes the shortened bits.
3. The method of claim 1 , wherein the firmware address information has a maximum reliability magnitude.
4. The method of claim 1 , wherein the shortened bits are all zeros, and the number of the shortened bits has a maximum reliability magnitude.
5. The method of claim 1 , wherein the meta information excludes address bits.
6. The method of claim 1 , wherein the meta information includes a field reserved for additional parity bits.
7. The method of claim 6 , wherein the additional parity bits include parity bits for a low density parity check (LDPC) code.
8. The method of claim 7 , wherein the additional parity bits include parity bits for high weight columns of the LDPC code.
9. The method of claim 6 , wherein the additional parity bits include parity bits for an inner code.
10. A system comprising:
a processor and a memory including instructions stored thereupon, wherein the instructions upon execution by the processor cause an encoder and a decoder to:
perform a write operation by the encoder and a read operation by the decoder,
wherein the write operation includes,
generating tagging information including address information and shortened bits added to the address information;
encoding a) user information, b) meta information, and c) the tagging information including the shortened bits added to the address information to generate parity information;
generating a codeword including the user information, the meta information and the parity information; and
storing the codeword in a memory device,
wherein the read operation includes,
reading the codeword read from the memory device;
adding, to the read codeword, tagging information including firmware (FW) address information in firmware to generate a modified codeword;
decoding, by a decoder, the modified codeword;
determining whether the decoding is successful based on decoding status;
determining an address mismatch when the firmware address information has been changed by the decoder; and
reporting the address mismatch to the firmware.
11. The system of claim 10 , wherein the address information is appended to the codeword and includes the shortened bits.
12. The system of claim 10 , wherein the firmware address information has a maximum reliability magnitude.
13. The system of claim 10 , wherein the shortened bits are all zeros, and the number of the shortened bits has a maximum reliability magnitude.
14. The system of claim 10 , wherein the meta information excludes address bits.
15. The system of claim 10 , wherein the meta information includes a field reserved for additional parity bits.
16. The system of claim 15 , wherein the additional parity bits include parity bits for a low density parity check (LDPC) code.
17. The system of claim 16 , wherein the additional parity bits include parity bits for high weight columns of the LDPC code.
18. The system of claim 15 , wherein the additional parity bits include parity bits for an inner code.
19. A method for generating a codeword for use in a memory system including a memory device, the method comprising:
generating tagging information including address information and shortened bits added to the address information;
encoding a) user information, b) meta information, and c) the tagging information including the shortened bits added to the address information to generate parity information;
including the user information, the meta information, the parity information and the shortened bits in the codeword; and
storing the codeword in the memory device,
wherein
the number of the shortened bits has a maximum reliability magnitude, and
the address information is appended in the codeword by the shortened bits.