IP Library › Granted Patent US 12,353,345
Granted Patent B2
US 12,353,345 · App. 18/338,466 · Granted Jul 8, 2025

Multi-path universal asynchronous transceiver and transmission method thereof

Inventors: GuoFeng Zhang (Suzhou, CN); YingXue Wang (Suzhou, CN); Hui Shen (Suzhou, CN); ZhaoMing Li (Suzhou, CN)
Assignee: REALTEK SEMICONDUCTOR CORP.
G06F13/366G06F13/1673G05B2219/33182
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,353,345
App. No.
18/338,466
Granted
Jul 8, 2025
Kind
B2
Abstract

The present disclosure provides a multi-path universal asynchronous transceiver (UART) and transmission method thereof. The multi-path UART comprises a first buffer, a second buffer, and a tx aggregation and arbitration circuit respectively coupled to the first buffer and the second buffer and presets a predetermined threshold. The tx aggregation and arbitration circuit polls the first buffer and the second buffer according to the predetermined threshold, and executes an arbitration procedure on the first buffer and the second buffer to obtain at least one of first log information packet and at least one of second log information packet correspondingly. Thus, when inputting a plurality of log sources, it is not necessary to have a plurality of output pins and to avoid disorder caused by the cross-influence of multiple log information for resource conservation and providing log information correctness.

Claims (32)

1. A multi-path universal asynchronous transceiver, comprising:

a first buffer caching at least one of first log information;

a second buffer caching at least one of second log information; and

a tx aggregation and arbitration circuit respectively coupled to the first buffer and the second buffer, and having a predetermined threshold;

wherein the tx aggregation and arbitration circuit: polls the first buffer and the second buffer according to the predetermined threshold; performs an arbitration procedure between the first buffer and the second buffer to obtain at least one of first log information packet and at least one of second log information packet correspondingly,

wherein the at least one of first log information packet and the at least one of second log information packet respectively comprise a header; the header comprises a synchronous pattern data, a path number data, and a checksum data.

2. The multi-path universal asynchronous transceiver according to claim 1 , further comprising:

a transmission buffer, coupled to the tx aggregation and arbitration circuit, receiving the at least one of first log information packet and the at least one of second log information packet; and

a transmitting circuit, coupled to the transmission buffer, configured to transmit the at least one of first log information packet and the at least one of second log information packet.

3. The multi-path universal asynchronous transceiver according to claim 2 , wherein the transmission buffer has a memory capacity; the tx aggregation and arbitration circuit compares at least one of received first log information packet and at least one of received second log information packet with the memory capacity to determine whether the receiving of the at least one of first log information and the at least one of second log information can be stopped.

4. The multi-path universal asynchronous transceiver according to claim 1 , wherein the tx aggregation and arbitration circuit compares the at least one of the first log information and the at least one of second log information with the predetermined threshold to determine whether the at least one of the first log information and the at least one of second log information conforms to the predetermined threshold; if so, the at least one of the first log information packet and the at least one of second log information packet be generated.

5. The multi-path universal asynchronous transceiver according to claim 4 , wherein the predetermined threshold is one of an information data volume and a time data.

6. The multi-path universal asynchronous transceiver according to claim 5 , wherein the tx aggregation and arbitration circuit compares a first data volume of the at least one of first log information and a second data volume of the at least one of second log information to determine whether the first data volume and the second data volume is greater than the information data volume; if so, the at least one of the first log information packet and the at least one of second log information packet be generated.

7. The multi-path universal asynchronous transceiver according to claim 6 , wherein the second buffer further comprises:

a second counter coupled to the tx aggregation and arbitration circuit and generating a second time data;

wherein, when the tx aggregation and arbitration circuit generates the at least one of second log information packet, the second time data is counted, and the tx aggregation and arbitration circuit compares the second time data according to the time data to determine whether the second time data is greater than the time data; if so in response to the second time data being greater than the time data, permitting the at least one of second log information packet to be generated.

8. The multi-path universal asynchronous transceiver according to claim 7 , wherein the tx aggregation and arbitration circuit clears the first time data and the second time data to return the first time data and the second time data to zero.

9. The multi-path universal asynchronous transceiver according to claim 5 , wherein the first buffer further comprises:

a first counter coupled to the tx aggregation and arbitration circuit and generating a first time data;

wherein, when the tx aggregation and arbitration circuit generates the at least one of first log information packet, the first time data is counted, and the tx aggregation and arbitration circuit compares the first time data according to the time data to determine whether the first time data is greater than the time data; in response to the first time data being greater than the time data, permitting the at least one of first log information packet to be generated.

10. The multi-path universal asynchronous transceiver according to claim 1 , wherein the header further comprises a payload length data.

11. A multi-path universal asynchronous transmission method, applied by a multi-path universal asynchronous transceiver, which comprises a first buffer, a second buffer, and a tx aggregation and arbitration circuit, the first buffer and the second buffer respectively configured to cache at least one of first log information and at least one of second log information; wherein, the multi-path universal asynchronous transmission method comprises:

presetting a predetermined threshold;

polling the first buffer and the second buffer according to the predetermined threshold;

performing an arbitration procedure between the first buffer and the second buffer to obtain at least one of first log information packet and at least one of second log information packet correspondingly;

wherein the at least one of first log information packet and the at least one of second log information packet respectively comprise a header, which comprises a synchronous pattern data, a path number data, and a checksum data.

12. The multi-path universal asynchronous transmission method according to claim 11 , wherein the header further comprises a payload length data.

13. The multi-path universal asynchronous transmission method according to claim 11 , further comprising:

comparing the at least one of first log information and the at least one of second log information with the predetermined threshold to determine whether the at least one of the first log information and the at least one of second log information conforms to the predetermined threshold; in response to the first log information and the at least one of second log information exceeding the predetermined threshold, the at least one of first log information packet and the at least one of second log information packet can be generated.

14. The multi-path universal asynchronous transmission method according to claim 11 , wherein the predetermined threshold is an information data volume and a time data.

15. The multi-path universal asynchronous transmission method according to claim 14 , further comprising:

comparing a second data volume of the at least one of first log information and a second data volume of the at least one of second log information with the information data volume to determine whether the first data volume and the second data volume is greater than the information data volume; in response to the first data volume and the second data volume being greater than the information data volume, the at least one of first log information packet and the at least one of second log information packet can be generated.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 14, 2024
From: SUZHOU PANKORE INTEGRATED CIRCUIT TECHNOLOGY CO. LTD.
To: REALTEK SEMICONDUCTOR CORP.
Reel/Frame 068884/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2023
From: ZHANG, GUOFENG; WANG, YINGXUE; SHEN, HUI; LI, ZHAOMING
To: SUZHOU PANKORE INTEGRATED CIRCUIT TECHNOLOGY CO. LTD.
Reel/Frame 064010/0971 →
Priority Claims (1)
CN 202211101254.3 · Sep 9, 2022 · national
Continuity (1)
Related Publication 20240086351A1 · Mar 14, 2024
References Cited (12)
US 6122279A · Milway et al. · 2000 [cited by applicant]
US 7508831B1 · Yeluri · 2009 [cited by examiner]
US 7830889B1 · Lemaire et al. · 2010 [cited by applicant]
US 7996704B2 · Chen · 2011 [cited by applicant]
US 8139481B2 · Laulainen · 2012 [cited by applicant]
US 20090262645A1 · Laulainen · 2009 [cited by examiner]
CN 101567851A · 2009 [cited by applicant]
CN 107733689A · 2018 [cited by applicant]
CN 111124317A · 2020 [cited by applicant]
TW 346715B · 1998 [cited by applicant]
TW 200910786A · 2009 [cited by applicant]
“A study on approaching 100% throughput input queueing switches”; NSC 91-2213-E-006-053; 92-07-31; pp. 1-5. [cited by applicant]