Low-power boot-up for memory systems

1. A memory system, comprising:

a first communication interface comprising a plurality of conductive paths;

a second communication interface comprising a first conductive path and a second conductive path; and

a controller associated with the memory system, wherein the controller is configured to cause the memory system to:

receive, over the first conductive path, a first indication to boot-up the memory system and the first communication interface associated with the memory system;

receive, over the second conductive path, a second indication of whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication, wherein a value of the second indication is based least in part on whether a charge state of a power supply is sufficient to activate the memory system and the first communication interface in the high-power mode, and wherein receiving the second indication over the second conductive path of the second communication interface instead of the first communication interface prevents the memory system from entering a power reset loop when the charge state of the power supply is insufficient to activate the first communication interface in the high-power mode; and

boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

2. The memory system of claim 1 , wherein the controller is further configured to cause the memory system to:

monitor a power input of the memory system;

determine whether the power input satisfies a threshold; and

switch from the low-power mode to the high-power mode based at least in part on the power input satisfying the threshold.

3. The memory system of claim 1 , wherein:

the second indication indicates whether to perform the boot-up operation of the memory system using a low-speed mode or a high-speed mode; and

booting the memory system is performed according to the low-speed mode or the high-speed mode based at least in part on receiving the second indication.

4. The memory system of claim 3 , wherein:

the second indication indicates to perform the boot-up operation using the low-power mode and the low-speed mode, and

the memory system is booted according to the low-power mode and the low-speed mode.

5. The memory system of claim 3 , wherein:

the second indication indicates to perform the boot-up operation using the high-power mode; and

the memory system is booted according to the high-power mode and the high-speed mode.

6. The memory system of claim 3 , wherein the controller is further configured to cause the memory system to:

monitor a power input of the memory system;

determine whether the power input satisfies a threshold; and

switch from the low-power mode to the high-power mode and from the low-speed mode to the high-speed mode based at least in part on the power input satisfying the threshold.

7. The memory system of claim 1 , wherein the controller is further configured to cause the memory system to:

receive, over a third conductive path, a third indication whether to perform the boot-up operation of the memory system using a low-speed mode or a high-speed mode based at least in part on receiving the first indication, wherein booting the memory system is performed according to the low-speed mode or the high-speed mode based at least in part on receiving the third indication.

8. The memory system of claim 7 , wherein:

the second indication indicates to perform the boot-up operation using the low-power mode;

the third indication indicates to perform the boot-up operation using the low-speed mode; and

the memory system is booted according to the low-power mode and the low-speed mode based at least in part on the second indication and the third indication.

9. The memory system of claim 7 , wherein:

the second indication indicates to perform the boot-up operation using the high-power mode;

the third indication indicates to perform the boot-up operation using the high-speed mode; and

the memory system is booted according to the high-power mode and the high-speed mode based at least in part on the second indication and the third indication.

10. The memory system of claim 7 , wherein the controller is further configured to cause the memory system to:

monitor a power input of the memory system;

determine whether the power input satisfies a threshold; and

switch from the low-power mode to the high-power mode and from the low-speed mode to the high-speed mode based at least in part on the power input satisfies the threshold.

11. The memory system of claim 1 , wherein:

the first conductive path is coupled with the power supply, wherein the power supply is configured to provide the first indication.

12. The memory system of claim 11 , wherein the power supply comprises a voltage common collector (VCC) pin.

13. The memory system of claim 1 , wherein:

the memory system comprises an integrated circuit configured to receive the first indication and the second indication.

14. The memory system of claim 13 , wherein the integrated circuit comprises an application-specific integrated circuit (ASIC).

15. The memory system of claim 1 , wherein:

the first communication interface comprises an open NAND flash interface (ONFI), and

the second communication interface comprises a universal flash system (UFS) interface.

16. The memory system of claim 1 , wherein the second conductive path comprises a general-purpose input/output (GPIO) pin.

17. The memory system of claim 1 , wherein the second conductive path comprises a vendor specific function (VSF) pin.

18. The memory system of claim 1 , wherein the second conductive path comprises a link startup speed (LSS) pin.

19. The memory system of claim 1 , wherein the high-power mode comprises booting-up the memory system using a power budget that is greater than 500 mA.

20. The memory system of claim 1 , wherein the high-power mode comprises booting-up the memory system using a power budget that is greater than 800 mA.

21. The memory system of claim 1 , wherein the low-power mode comprises booting-up the memory system using a power budget that is less than or equal to 500 mA.

22. The memory system of claim 1 , wherein the controller is further configured to cause the memory system to:

adjust a performance parameter of a plurality of performance parameters of the memory system in response to the memory system being booted according to the low-power mode, wherein the plurality of performance parameters comprises a clock speed and a communication rate associated with the first communication interface, wherein adjusting the performance parameter further comprises reducing the clock speed and the communication rate.

23. A method, comprising:

receiving, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, the first communication interface comprising a plurality of conductive paths;

receiving, over a second conductive path of the second communication interface, a second indication of whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication, wherein a value of the second indication is based least in part on whether a charge state of a power supply is sufficient to activate the memory system and the first communication interface in the high-power mode, and wherein receiving the second indication over the second conductive path of the second communication interface instead of the first communication interface prevents the memory system from entering a power reset loop when the charge state of the power supply is insufficient to activate the first communication interface in the high-power mode; and

booting the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.

24. The method of claim 23 , further comprising:

monitoring a power input of the memory system;

determining whether the power input satisfies a threshold; and

switching from the low-power mode to the high-power mode based at least in part on the power input satisfying the threshold.

25. A non-transitory computer-readable medium storing code, the code comprising instructions executable by a processor to:

receive, over a first conductive path of a second communication interface, a first indication to boot-up a memory system and a first communication interface associated with the memory system, the first communication interface comprising a plurality of conductive paths;

receive, over a second conductive path of the second communication interface, a second indication of whether to perform a boot-up operation of the memory system using a low-power mode or a high-power mode based at least in part on receiving the first indication, wherein a value of the second indication is based least in part on whether a charge state of a power supply is sufficient to activate the memory system and the first communication interface in the high-power mode, and wherein receiving the second indication over the second conductive path of the second communication interface instead of the first communication interface prevents the memory system from entering a power reset loop when the charge state of the power supply is insufficient to activate the first communication interface in the high-power mode; and

boot the memory system according to the low-power mode or the high-power mode based at least in part on receiving the second indication.