Standard cell layout for better routability
A method of fabricating an integrated circuit is disclosed. The method comprises defining a multi-layer semiconductor device structure on a substrate using standard cells, defining an input port on the M0OD or PO layer of the semiconductor device structure and an output port on the M0OD layer, and defining a metal-1 layer over the M0OD and PO layers, the metal-1 layer having a first set of conduction paths and a second set of conduction paths. The method further comprises defining a metal-2 layer over the metal-1 layer and configuring the first set of metal-1 conduction paths and the metal-2 conduction paths to interconnect circuit components in different cells, wherein inter cell connections in the semiconductor device structure are made using the first set of metal-1 conduction paths or a combination of the first set of metal-1 and the metal-2 conduction paths.
1. A device comprising:
a plurality of cells arranged on a substrate;
an input port fabricated on a metal-0 oxide diffusion (M0OD) or polysilicon (PO) layer of the plurality of cells;
a metal-1 layer over the input port and having a set of metal-1 conduction paths, at least one of which extends across multiple cells of the plurality of cells;
a metal-2 layer above the metal-1 layer; and
a metal-3 layer above the metal-2 layer, wherein no inter cell connection is made using a metal-3 conduction path in the metal-3 layer.
2. The device of claim 1 , further comprising an output port defined on the M0OD layer.
3. The device of claim 1 , wherein all inter cell connections in the device are made using the set of metal-1 conduction paths or a combination of the set of metal-1 conduction paths and a first set of metal-2 conduction paths.
4. The device of claim 1 , wherein a second set of metal-1 conduction paths and a second set of metal-2 conduction paths are configured to interconnect circuit components within the same cell.
5. The device of claim 1 , further comprising a set of metal-2 conduction paths, wherein each of the set of metal-1 conduction paths and each of the set of metal-2 conduction paths are associated with a respective rule specifying which type of interconnection path can be made using sets of metal-1 and metal-2 conduction paths.
6. The device of claim 1 , further comprising:
a first via connected between a metal-2 conduction path and a first of the metal-1 conduction path; and
a second via connected between the metal-2 conduction path and a second metal-1 conduction path.
7. The device of claim 1 , further comprising a third via connected between a metal-1 conduction path and a circuit component.
8. The device of claim 1 , wherein the metal-1 layer comprises up to six horizontal direction metal-1 conduction paths per cell over the M0OD layer and the PO layer.
9. The device of claim 1 , wherein the input port or an output port is defined on the metal-1 layer.
10. The device of claim 1 , wherein the metal-2 layer includes a set of metal-2 conduction paths.
11. A circuit comprising:
a plurality of cells arranged on a substrate;
an output port fabricated on the metal-0 oxide diffusion (M0OD) layer of the plurality of cells;
a metal-1 layer over the output port and having a set of metal-1 conduction paths, at least one of which extends across multiple cells of the plurality of cells;
a metal-2 layer above the metal-1 layer; and
a metal-3 layer above the metal-2 layer, wherein no inter cell connection is made using a metal-3 conduction path in the metal-3 layer.
12. The circuit of claim 11 , further comprising an input port defined on the M0OD layer or a polysilicon (PO) layer.
13. The circuit of claim 11 , wherein all inter cell connections are made using the metal-1 conduction paths or a combination of the set of metal-1 conduction paths and a first set of metal-2 conduction paths.
14. The circuit of claim 11 , wherein a second set of metal-1 conduction paths and a second set of metal-2 conduction paths are configured to interconnect circuit components within the same cell.
15. The circuit of claim 11 , further comprising a set of metal-2 conduction paths, wherein each of the set of metal-1 conduction paths and each of the set of metal-2 conduction paths are associated with a respective rule specifying which type of interconnection path can be made using such sets of metal-1 and metal-2 conduction paths.
16. The circuit of claim 11 , further comprising:
a first via connected between a metal-2 conduction path and a first metal-1 conduction path; and
a second via connected between the metal-2 conduction path and a second metal-1 conduction path.
17. The circuit of claim 11 , wherein a third via is connected between a metal-1 conduction path and a circuit component.
18. The circuit of claim 11 , wherein the metal-1 layer comprises up to six horizontal direction metal-1 conduction paths per cell over the M0OD layer and a polysilicon (PO) layer.
19. The device of claim 11 , wherein the metal-2 layer includes a set of metal-2 conduction paths.
20. A device comprising:
a plurality of cells arranged on a substrate;
first and second power rails;
a metal-1 layer over a metal-0 oxide diffusion (M0OD) or polysilicon (PO) layer of the plurality of cells and having a set of metal-1 conduction paths, at least one of which extends across multiple cells of the plurality of cells;
a metal-2 layer above the metal-1 layer; and
a metal-3 layer above the metal-2 layer, wherein no inter cell connection is made using a metal-3 conduction path in the metal-3 layer.