Memory device including memory chip and peripheral memory chip and method of manufacturing the memory device
A memory device includes a memory chip including a memory cell array connected to first word lines and first bit lines, first word line bonding pads respectively connected to the first word lines, and first bit line bonding pads respectively connected to the first bit lines, and a peripheral circuit chip, wherein the peripheral circuit chip includes a test cell array connected to second word lines and second bit lines, second word line bonding pads respectively connected to the first word line bonding pads, second bit line bonding pads respectively connected to the first bit line bonding pads, and a peripheral circuit connected to the second word line bonding pads and the second word lines or the second bit line bonding pads and the second bit lines.
1. A memory device, comprising:
a memory chip including
a memory cell array connected to first word lines and first bit lines,
first word line bonding pads respectively connected to the first word lines, and
first bit line bonding pads respectively connected to the first bit lines; and
a peripheral circuit chip, wherein the peripheral circuit chip includes
a test cell array connected to second word lines and second bit lines,
second word line bonding pads respectively connected to the first word line bonding pads,
second bit line bonding pads respectively connected to the first bit line bonding pads, and
a peripheral circuit connected to the second word line bonding pads and the second word lines, or the second bit line bonding pads and the second bit lines,
wherein the peripheral circuit includes a row decoder connected to the memory cell array through the first and second word line bonding pads and the first word lines and connected to the test cell array through the second word lines.
2. The memory device of claim 1 , wherein the peripheral circuit further includes a page buffer connected to the memory cell array through the first and second bit line bonding pads and the first bit lines and connected to the test cell array through the second bit lines.
3. The memory device of claim 1 , wherein the first and second word line bonding pads and the first and second bit line bonding pads include copper.
4. The memory device of claim 1 , wherein
the first and second word line bonding pads are connected to each other based on a bonding manner, and
the first and second bit line bonding pads are connected to each other based on the bonding manner.
5. The memory device of claim 1 , wherein the memory cell array is disposed above the test cell array in a vertical direction.
6. The memory device of claim 1 , wherein the peripheral circuit chip is vertically connected to the memory chip via the first and second word line bonding pads and the first and second bit line bonding pads.
7. The memory device of claim 1 , wherein
the memory cell array includes a three-dimensional (3D) cell array including a plurality of memory blocks, and
each memory block of the plurality of memory blocks includes a plurality of vertical NAND strings.
8. The memory device of claim 1 , wherein
the test cell array includes a two-dimensional (2D) cell array including at least one test block, and
the at least one test block includes a plurality of planar NAND strings.
9. A memory device, comprising:
a three-dimensional (3D) memory cell array connected to first word lines and first bit lines;
first word line bonding pads respectively connected to the first word lines;
first bit line bonding pads respectively connected to the first bit lines;
a two-dimensional (2D) test cell array connected to second word lines and second bit lines;
second word line bonding pads respectively connected to the first word line bonding pads;
second bit line bonding pads respectively connected to the first bit line bonding pads; and
a peripheral circuit connected to the second word line bonding pads and the second word lines, or the second bit line bonding pads and the second bit lines,
wherein the 3D memory cell array is disposed above the 2D test cell array in a vertical direction.
10. The memory device of claim 9 , wherein the 2D test cell array and the peripheral circuit are vertically connected to the 3D memory cell array via the first and second word line bonding pads and the first and second bit line bonding pads.
11. The memory device of claim 9 , wherein
the 3D memory cell array includes a plurality of memory blocks, and
each memory block of the plurality of memory blocks includes a plurality of vertical NAND strings.
12. The memory device of claim 9 , wherein
the 2D test cell array includes at least one test block, and
the at least one test block includes a plurality of planar NAND strings.
13. The memory device of claim 12 , wherein the 3D memory cell array, the first word line bonding pads, and the first bit line bonding pads are included in a memory chip,
the 2D test cell array, the second word line bonding pads, the second bit line bonding pads and the peripheral circuit are included in a peripheral circuit chip, and
the peripheral circuit is configured to perform an electrical die sorting (EDS) process before the peripheral circuit chip is bonded to the memory chip, wherein the EDS process inspects whether or not the test cell array and the peripheral circuit electrically operate.
14. The memory device of claim 13 , wherein the 2D test cell array further includes at least one information data block storing information data that is set through the EDS process.
15. The memory device of claim 14 , wherein the memory chip is configured to perform an information data read (IDR) operation on the at least one information data block, after the memory chip is bonded to the peripheral circuit chip.