Multi-level buck converter and associate control circuit thereof

1. A control circuit for controlling a multi-level buck converter having N pairs of switches serially connected between an input terminal and a logic ground, and wherein N is an integer equal to or greater than 2, the control circuit comprising:

a comparing circuit configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal;

a selecting circuit configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal; and

a delay circuit configured to delay the N set signals to provide N delay set signals to control the N pairs of switches when the output voltage signal falls in

(

1

±

k

⁢

%

)

×

1

N

 of an input voltage signal of the multi-level buck converter,

(

1

±

k

⁢

%

)

×

2

N

 of the input voltage signal, . . . , or

(

1

±

k

⁢

%

)

×

N

-

1

N

 of the input voltage signal, wherein k is a proportional coefficient.

2. The control circuit of claim 1 , wherein the delay circuit comprises:

a voltage divider configured to receive the input voltage signal to generate N−1 dividing voltage signals, wherein for each i=1, . . . , N−1, the i th dividing voltage signal of the N−1 dividing voltage signals is equal to

i

N

 of the input voltage signal;

N−1 hysteresis comparators configured to generate N−1 determining signals, wherein for each i=1, . . . , N−1, the i th hysteresis comparator is configured to receive the output voltage signal and the i th dividing voltage signal, and further configured to compare the output voltage signal with the i th dividing voltage signal to generate the i th determining signal of the N−1 determining signal;

an OR logic gate configured to receive the N−1 determining signals, and configured to conduct a logic OR operation of the N−1 determining signals to generate a delay enable signal; and

a plurality of delay modules, wherein each of the plurality of delay modules is configured to receive the delay enable signal and one corresponding set signal of the N set signals, and further configured to generate one corresponding delay set signal based on the delay enable signal and the corresponding set signal.

3. The control circuit of claim 2 , wherein when N is an odd number, the quantity of the delay modules is equal to (N−1)/2, and when N is an even number, the quantity of the delay modules is equal to N/2.

4. The control circuit of claim 1 , wherein when N is an odd number, for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i−1) th set signal of the N set signals to provide the (2i−1) th delay set signal of the N delay set signals.

5. The control circuit of claim 1 , wherein when N is an odd number, for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i+1) th set signal of the N set signals to provide the (2i+1) th delay set signal of the N delay set signals.

6. The control circuit of claim 1 , wherein when N is an odd number, for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i) th set signal of the N set signals to provide the (2i) th delay set signal of the N delay set signals.

7. The control circuit of claim 1 , wherein when N is an even number, for each i=1, . . . , N/2, the delay circuit is configured to delay the (2i−1) th set signal of the N set signals to provide the (2i−1) th delay set signal of the N delay set signals.

8. The control circuit of claim 1 , wherein when N is an even number, for each i=1, . . . , N/2, the delay circuit is configured to delay the (2i) th set signal of the N set signals to provide the (2i) th delay set signal of the N delay set signals.

9. The control circuit of claim 1 , wherein the proportional coefficient k is smaller than 10.

10. The control circuit of claim 1 , further comprising:

N COT controllers, wherein for each i=1, 2, . . . , N, the i th COT controller is configured to receive the i th delay set signal of the N delay set signals, the output voltage signal and the input voltage signal, and based on the i th delay set signal, the output voltage signal and the input voltage signal, the i th COT controller is further configured to generate an i th control signal to control the i th pair of switches of the N pairs of switches to perform a complementary on and off switching.

11. A multi-level buck converter, comprising:

N pairs of switches serially connected between an input terminal and a logic ground, wherein N is an integer equal to or greater than 2;

a comparing circuit configured to receive a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter, and further configured to compare the voltage feedback signal with the reference signal to generate a comparing signal;

a selecting circuit configured to receive the comparing signal, and further configured to generate N set signals based on the comparing signal; and

a delay circuit configured to delay the N set signals to provide N delay set signals to control the N pairs of switches when the output voltage signal falls in

(

1

±

k

⁢

%

)

×

1

N

 of an input voltage signal of the multi-level buck converter,

(

1

±

k

⁢

%

)

×

2

N

 of the input voltage signal, . . . , or

(

1

±

k

⁢

%

)

×

N

-

1

N

 of the input voltage signal, wherein k is a proportional coefficient.

12. The multi-level buck converter of claim 11 , wherein the delay circuit comprises:

a voltage divider configured to receive the input voltage signal to generate N−1 dividing voltage signals, wherein for each i=1, . . . , N−1, the i th dividing voltage signal of the N−1 dividing voltage signals is equal to

i

N

 of the input voltage signal;

N−1 hysteresis comparators configured to generate N−1 determining signals, wherein for each i=1, . . . , N−1, the i th hysteresis comparator is configured to receive the output voltage signal and the i th dividing voltage signal, and further configured to compare the output voltage signal with the i th dividing voltage signal to generate the i th determining signal of the N−1 determining signal;

an OR logic gate configured to receive the N−1 determining signals, and configured to conduct a logic OR operation of the N−1 determining signals to generate a delay enable signal; and

a plurality of delay modules, wherein each of the plurality of delay modules is configured to receive the delay enable signal and one corresponding set signal of the N set signals, and further configured to generate one corresponding delay set signal based on the delay enable signal and the corresponding set signal.

13. The multi-level buck converter of claim 12 , wherein when N is an odd number, the quantity of the delay modules is equal to (N−1)/2, when N is an even number, the quantity of the delay modules is equal to N/2.

14. The multi-level buck converter of claim 11 , wherein when N is an odd number, for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i−1) th set signal of the N set signals to provide the (2i−1) th delay set signal of the N delay set signals.

15. The multi-level buck converter of claim 11 , wherein when N is an odd number, for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i+1) th set signal of the N set signals to provide the (2i+1) th delay set signal of the N delay set signals.

16. The multi-level buck converter of claim 11 , wherein when N is an odd number, for each i=1, . . . , (N−1)/2, the delay circuit is configured to delay the (2i) th set signal of the N set signals to provide the (2i) th delay set signal of the N delay set signals.

17. The multi-level buck converter of claim 11 , wherein when N is an even number, for each i=1, . . . , N/2, the delay circuit is configured to delay the (2i−1) th set signal of the N set signals to provide the (2i−1) th delay set signal of the N delay set signals.

18. The multi-level buck converter of claim 11 , wherein when N is an even number, for each i=1, . . . , N/2, the delay circuit is configured to delay the (2i) th set signal of the N set signals to provide the (2i) th delay set signal of the N delay set signals.

19. A control method for controlling a multi-level buck converter having N pairs of switches serially connected between an input terminal and a logic ground, and wherein N is an integer equal to or greater than 2, the control method comprising:

generating a comparing signal based on a comparison between a reference signal and a voltage feedback signal indicative of an output voltage signal of the multi-level buck converter;

generating N set signals based on the comparing signal; and

providing N delay set signals to control the N pairs of switches by delaying the N set signals when the output voltage signal falls in

(

1

±

k

⁢

%

)

×

1

N

 of an input voltage signal of the multi-level buck converter,

(

1

±

k

⁢

%

)

×

2

N

 of the input voltage signal, . . . , or

(

1

±

k

⁢

%

)

×

N

-

1

N

 of the input voltage signal, wherein k is a proportional coefficient.

20. The control method of claim 19 , wherein the step of providing N delay set signals comprises:

generating N−1 dividing voltage signals based on the input voltage signal, wherein for each i=1, . . . , N−1, the i th dividing voltage signal of the N−1 dividing voltage signals is equal to

i

N

 of the input voltage signal;

generating N−1 determining signals based on the N−1 dividing voltage signals, wherein for each i=1, . . . , N−1, the i th determining signal is generated based on a comparison between the i th dividing voltage signal and the output voltage signal;

generating a delay enable signal based on the N−1 determining signals; and

providing the N delay set signals by delaying the N set signals when the delay enable signal is in an active state.