Interleaved analog-to-digital converter (ADC) gain calibration
An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.
1. An integrated circuit, comprising:
a set of interleaved analog-to-digital converters (ADCs); and
a full-scale reference generation circuit comprising an analog circuit and digital-to-analog converters (DACs), wherein the analog circuit is configured to generate full-scale reference voltages of full scales of each ADC in the set of interleaved ADCs,
wherein the DACs are configured to provide variable currents that, at least in part, specify the full-scale reference voltages,
wherein the variable currents correspond to full-scale corrections of the full scales of the set of interleaved ADCs,
wherein the full-scale reference voltages correspond to the variable currents and a fixed current, and
wherein at least a portion of the full-scale reference generation circuit is common to or shared by the set of interleaved ADCs.
2. The integrated circuit of claim 1 , wherein the analog circuit comprises full-scale reference generator circuits configured to generate the full-scale reference voltages for corresponding ADCs of the set of interleaved ADCs; and
wherein the full-scale reference generator circuits comprise open-loop buffers.
3. The integrated circuit of claim 1 , wherein the integrated circuit comprises a calibration circuit; and
wherein the calibration circuit is configured to determine the full-scale corrections and is configured to provide feedback to the set of interleaved ADCs via the full-scale reference generation circuit.
4. The integrated circuit of claim 1 , wherein the integrated circuit comprises a full-scale reference generator replica circuit that is configured to provide the fixed current.
5. The integrated circuit of claim 4 , where the full-scale reference generator replica circuit is common to or shared by the full-scale reference generator circuits.
6. The integrated circuit of claim 4 , where the full-scale reference generator replica circuit comprises a second open-loop buffer that matches open-loop buffers in the full-scale reference generator circuits.
7. The integrated circuit of claim 1 , wherein a given full-scale reference voltage of a given interleaved ADC corresponds to a sum of a given variable current and the fixed current.
8. The integrated circuit of claim 1 , where the full-scale reference voltages are bipolar.
9. The integrated circuit of claim 8 , where a given full-scale reference voltage comprises a first voltage and a second voltage that jointly specify the given full-scale reference voltage.
10. The integrated circuit of claim 9 , where the first voltage corresponds to a given full-scale correction to a given full scale of a given interleaved ADC.
11. The integrated circuit of claim 9 , where the second voltage is a supply voltage of the integrated circuit.
12. The integrated circuit of claim 1 , where the full-scale reference voltages are independently or separately generated by the full-scale reference generation circuit.
13. A system, comprising:
a set of interleaved analog-to-digital converters (ADCs); and
a full-scale reference generation circuit comprising an analog circuit and digital-to-analog converters (DACs), wherein the analog circuit is configured to generate full-scale reference voltages of full scales of each ADC in the set of interleaved ADCs,
wherein the DACs are configured to provide variable currents that, at least in part, specify the full-scale reference voltages,
wherein the variable currents correspond to full-scale corrections of the full scales of the set of interleaved ADCs,
wherein the full-scale reference voltages correspond to the variable currents and a fixed current, and
wherein at least a portion of the full-scale reference generation circuit is common to or shared by the set of interleaved ADCs.
14. The system of claim 13 , wherein the analog circuit comprises full-scale reference generator circuits configured to generate the full-scale reference voltages for corresponding ADCs of the set of interleaved ADCs; and
wherein the full-scale reference generator circuits comprise open-loop buffers.
15. The system of claim 13 , wherein the system comprises a calibration circuit; and
wherein the calibration circuit is configured to determine the full-scale corrections and is configured to provide feedback to the set of interleaved ADCs via the full-scale reference generation circuit.
16. The system of claim 13 , wherein a given full-scale reference voltage of a given interleaved ADC corresponds to a sum of a given variable current and the fixed current.
17. A method for generating full-scale reference voltages, comprising:
by a full-scale reference generation circuit comprising an analog circuit:
receiving, from digital-to-analog converters (DACs), variable currents that, at least in part, specify the full-scale reference voltages; and
generating, using the analog circuit and based at least in part on the variable currents, the full-scale reference voltages of full scales of each analog-to-digital converter (ADC) in a set of interleaved ADCs, wherein the variable currents correspond to full-scale corrections of the full scales of the set of interleaved ADCs, and
wherein at least a portion of the full-scale reference generation circuit is common to or shared by the set of interleaved ADCs.
18. The method of claim 17 , wherein the full-scale reference voltages are generated by corresponding full-scale reference generator circuits in the full-scale reference generation circuit; and
wherein the full-scale reference generator circuits comprise open-loop buffers.
19. The method of claim 17 , wherein, using a calibration circuit, the method comprises determining the full-scale corrections and providing feedback to the set of interleaved ADCs via the full-scale reference generation circuit.
20. The method of claim 17 , wherein a given full-scale reference voltage of a given interleaved ADC corresponds to a sum of a given variable current and the fixed current.