Semiconductor device and methods of manufacturing
View Patent ↗In some implementations, a buffer layer is formed under a source/drain region of a device. A shape of the buffer layer may include a curved top surface having a height that extends to increase coverage of nanosheets of a fin structure of the device. The shape also includes regions having widths that extend towards shallow trench isolation regions of the device. The shape reduces a likelihood of dopants diffusing from the source/drain region into a mesa region of the fin structure. As a result, a performance of the device may be increased by decreasing short channel effects, decreasing an off-current of the device, and decreasing leakage within the device, among other examples.
1. A semiconductor device, comprising:
a plurality of nanostructure channels over a substrate,
wherein the plurality of nanostructure channels are arranged in a direction perpendicular to the substrate;
a gate structure wrapping around the plurality of nanostructure channels over the substrate;
a source/drain region adjacent to the plurality of nanostructure channels and the gate structure;
an inner spacer layer disposed between a top surface of a mesa region and a bottom nanostructure channel of the plurality of nanostructure channels; and
a buffer region under the source/drain region,
wherein a curved top surface of the buffer region includes an apex height that is greater relative to a height of a bottom surface of the inner spacer layer, and
wherein the apex height of the curved top surface is lesser relative to a height of a top surface of the inner spacer layer,
wherein a first distance, between the bottom surface of the inner spacer layer and a top surface of a top nanostructure channel, is less relative to a second distance, between the bottom surface of the inner spacer layer and a bottom depth of the buffer region.
2. The semiconductor device of claim 1 , wherein a distance between the apex height and the bottom surface of the inner spacer layer is in a range of approximately 50% to approximately 90% of a thickness of the inner spacer layer.
3. The semiconductor device of claim 1 , wherein the first distance is in a range of approximately 30 nanometers to approximately 80 nanometers.
4. The semiconductor device of claim 1 , wherein the second distance is in a range of approximately 10 nanometers to approximately 50 nanometers.
5. The semiconductor device of claim 1 , further comprising:
a plurality of hybrid fin structures, including a first hybrid fin structure and a second hybrid fin structure, adjacent to the bottom nanostructure channel,
wherein the buffer region is between the first hybrid fin structure and the second hybrid fin structure.
6. The semiconductor device of claim 5 , wherein:
a first portion of the buffer region extends into a first shallow trench isolation region between a first nanostructure channel, of the plurality of nanostructure channels, and the first hybrid fin structure,
wherein a second portion of the buffer region extends into a second shallow trench isolation region that is between the first nanostructure channel and the second hybrid fin structure.
7. A semiconductor device, comprising:
a bottom nanostructure channel over a substrate;
a first hybrid fin structure adjacent to a first side of the bottom nanostructure channel;
a second hybrid fin structure adjacent to a second side of the bottom nanostructure channel that is opposite the first side; and
a buffer region between the first hybrid fin structure and the second hybrid fin structure,
wherein a first portion of the buffer region extends into a first shallow trench isolation region between the first side of the bottom nanostructure channel and the first hybrid fin structure,
wherein a second portion of the buffer region extends into a second shallow trench isolation region that is between the second side of the bottom nanostructure channel and the second hybrid fin structure, and
wherein a curved top surface of the buffer region includes an apex height that is greater relative to a height of a top surface of the first shallow trench isolation region, greater relative to a height of a top surface of the second shallow trench isolation region, and lesser relative to a height of a bottom surface of the bottom nanostructure channel.
8. The semiconductor device of claim 7 , wherein the first portion of the buffer region extends from the first side of the bottom nanostructure channel towards the first shallow trench isolation region a distance that is in a range of approximately 3 nanometers to approximately 10 nanometers from the first side of the bottom nanostructure channel.
9. The semiconductor device of claim 7 , wherein the first portion of the buffer region extends into a liner on a sidewall of the first hybrid fin structure.
10. The semiconductor device of claim 7 , further comprising:
a bottom portion of a gate structure below the bottom nanostructure channel,
wherein the bottom portion of the gate structure wraps around a fin structure including the bottom nanostructure channel; and
a source/drain region above the buffer region,
wherein a shaped portion of the buffer region comprising the first portion, the second portion, and the curved top surface reduces a likelihood of dopants of the source/drain region from migrating into a mesa region below the bottom portion.
11. The semiconductor device of claim 10 , wherein the apex height of the curved top surface extends above a bottom surface of the bottom portion.
12. The semiconductor device of claim 10 , wherein a first width, from a side edge of the first portion to a side edge of the second portion, is greater relative to a second width of the source/drain region.
13. The semiconductor device of claim 12 , wherein the first width is greater relative to the second width in a range of approximately 1 nanometer to approximately 10 nanometers.
14. A semiconductor device, comprising:
a bottom nanostructure channel over a substrate;
a plurality of hybrid fin structures, including a first hybrid fin structure and a second hybrid fin structure, adjacent to the bottom nanostructure channel; and
a buffer region between the first hybrid fin structure and the second hybrid fin structure,
wherein at least one of:
a first portion of the buffer region extends into a first shallow trench isolation region between the bottom nanostructure channel and the first hybrid fin structure, or
a second portion of the buffer region extends into a second shallow trench isolation region that is between the bottom nanostructure channel and the second hybrid fin structure.
15. The semiconductor device of claim 14 , wherein the first portion of the buffer region extends a distance, from a first side of the bottom nanostructure channel towards the first shallow trench isolation region, that is in a range of approximately 3 nanometers to approximately 10 nanometers.
16. The semiconductor device of claim 14 , wherein the first portion of the buffer region extends into a liner on a sidewall of the first hybrid fin structure.
17. The semiconductor device of claim 14 , further comprising:
a gate structure comprising a bottom portion of the bottom nanostructure channel,
wherein the bottom portion of the gate structure wraps around a fin structure including the bottom nanostructure channel.
18. The semiconductor device of claim 14 , further comprising:
a source/drain region above the buffer region.
19. The semiconductor device of claim 18 , wherein a first width, from a side edge of the first portion to a side edge of the second portion, is greater relative to a second width of the source/drain region.
20. The semiconductor device of claim 19 , wherein the first width is greater relative to the second width in a range of approximately 1 nanometer to approximately 10 nanometers.