Semiconductor integrated circuit device
A terminal cell includes: third and fourth nanosheets formed at the same positions as first and second nanosheets, respectively, in the Y direction; and first and second dummy gate interconnects surrounding the peripheries of the third and fourth nanosheets, respectively, in the Y direction. Faces of the first and third nanosheets on one side in the Y direction are exposed from a first gate interconnect and the first dummy gate interconnect, respectively. Faces of the second and fourth nanosheets on one side in the Y direction are exposed from a second gate interconnect and the second dummy gate interconnect, respectively.
1. A semiconductor integrated circuit device comprising a plurality of cell rows each having a plurality of standard cells arranged in a first direction, wherein:
a first cell row, as one of the plurality of cell rows, includes a first standard cell having a logical function and a second standard cell having no logical function placed at at least one of both ends of the first cell row,
the first standard cell includes:
a first region that is a region for formation of a transistor of a first conductivity type,
a second region that is a region for formation of a transistor of a second conductivity type different from the first conductivity type and is adjacent to the first region in a second direction perpendicular to the first direction,
a first nanosheet extending in the first direction, formed in the first region,
a second nanosheet extending in the first direction, formed in the second region,
a first gate interconnect extending in the second direction, surrounding a periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions, and
a second gate interconnect extending in the second direction, surrounding a periphery of the second nanosheet in the second and third directions,
the second standard cell includes:
a third nanosheet extending in the first direction, formed at the same position as the first nanosheet in the second direction,
a fourth nanosheet extending in the first direction, formed at the same position as the second nanosheet in the second direction,
a first dummy gate interconnect extending in the second direction, surrounding a periphery of the third nanosheet in the second and third directions, and
a second dummy gate interconnect extending in the second direction, surrounding a periphery of the fourth nanosheet in the second and third directions,
in a first cross section cutting the first gate interconnect by a first plane defined by the second and third directions along the second direction, a face of the first nanosheet on a first side that is one side in the second direction is exposed from the first gate interconnect,
in a second cross section cutting the second gate interconnect by a second plane defined by the second and third directions along the second direction, a face of the second nanosheet on a second side that is one side in the second direction is exposed from the second gate interconnect,
in a third cross section cutting the first dummy gate interconnect by a third plane defined by the second and third directions along the second direction, a face of the third nanosheet on the first side in the second direction is exposed from the first dummy gate interconnect, and
in a fourth cross section cutting the second dummy gate interconnect by a fourth plane defined by the second and third directions along the second direction, a face of the fourth nanosheet on the second side in the second direction is exposed from the second dummy gate interconnect.
2. The semiconductor integrated circuit device of claim 1 , wherein
the first side is a side of the first nanosheet closer to the second region, and
the second side is a side of the second nanosheet closer to the first region.
3. The semiconductor integrated circuit device of claim 1 , wherein
the first side is a side of the first nanosheet farther from the second region, and
the second side is a side of the second nanosheet farther from the first region.
4. The semiconductor integrated circuit device of claim 1 , wherein:
the first standard cell further includes
a fifth nanosheet extending in the first direction, formed in the first region, and
a sixth nanosheet extending in the first direction, formed in the second region, the second standard cell further includes
a seventh nanosheet extending in the first direction, formed at the same position as the fifth nanosheet in the second direction, and
an eighth nanosheet extending in the first direction, formed at the same position as the sixth nanosheet in the second direction,
the first gate interconnect surrounds a periphery of the fifth nanosheet in the second and third directions,
the second gate interconnect surrounds a periphery of the sixth nanosheet in the second and third directions,
the first dummy gate interconnect surrounds a periphery of the seventh nanosheet in the second and third directions,
the second dummy gate interconnect surrounds a periphery of the eighth nanosheet in the second and third directions,
in the first cross section, a face of the fifth nanosheet on a side opposite to the first side in the second direction is exposed from the first gate interconnect,
in the second cross section, a face of the sixth nanosheet on a side opposite to the second side in the second direction is exposed from the second gate interconnect,
in the third cross section, a face of the seventh nanosheet on a side opposite to the first side in the second direction is exposed from the first dummy gate interconnect, and
in the fourth cross section, a face of the eighth nanosheet on a side opposite to the second side in the second direction is exposed from the second dummy gate interconnect.
5. The semiconductor integrated circuit device of claim 4 , wherein
third and fourth dummy gate interconnects extending in the second direction are formed along a cell boundary between the first and second standard cells,
the first gate interconnect and the first and third dummy gate interconnects are placed at an equal pitch in the first direction, and
the second gate interconnect and the second and fourth dummy gate interconnects are placed at an equal pitch in the first direction.
6. A semiconductor integrated circuit device comprising a plurality of cell rows each having a plurality of standard cells arranged in a first direction, the plurality of cell rows being arranged in a second direction perpendicular to the first direction, wherein:
the plurality of cell rows include a first cell row including a first standard cell having a logical function and a second cell row including a second standard cell having no logical function, the second cell row being placed in either one of both ends of the plurality of cell rows in the second direction,
the first standard cell includes
a first region that is a region for formation of a transistor of a first conductivity type,
a second region that is a region for formation of a transistor of a second conductivity type different from the first conductivity type and is adjacent to the first region in the second direction,
a first nanosheet extending in the first direction, formed in the first region,
a second nanosheet extending in the first direction, formed in the second region, and formed at the same position as the first nanosheet in the first direction,
a first gate interconnect extending in the second direction, surrounding a periphery of the first nanosheet in the second direction and in a third direction perpendicular to the first and second directions, and
a second gate interconnect extending in the second direction, surrounding a periphery of the second nanosheet in the second and third directions,
the second standard cell includes
a third nanosheet extending in the first direction, formed at the same position as the first nanosheet in the first direction, and formed adjacent to the first nanosheet in the second direction, and
a first dummy gate interconnect extending in the second direction, surrounding a periphery of the third nanosheet in the second and third directions, and
in a first cross section cutting the first gate interconnect by a first plane defined by the second and third directions along the second direction, a face of the first nanosheet on a first side that is one side in the second direction is exposed from the first gate interconnect,
in a second cross section cutting the second gate interconnect by a second plane defined by the second and third directions along the second direction, a face of the second nanosheet on a second side that is one side in the second direction is exposed from the second gate interconnect, and
in a third cross section cutting the first dummy gate interconnect by a third plane defined by the second and third directions along the second direction, faces of the first and third nanosheets opposed to each other are exposed from the first gate interconnect and the first dummy gate interconnect, respectively, or faces of the first and third nanosheets opposed to each other are not exposed from the first gate interconnect and the first dummy gate interconnect, respectively.
7. The semiconductor integrated circuit device of claim 6 , wherein
the first side is a side of the first nanosheet opposed to the third nanosheet, and
a face of the third nanosheet on a side opposed to the first nanosheet is exposed from the first dummy gate interconnect.
8. The semiconductor integrated circuit device of claim 6 , wherein
the first side is a side of the first nanosheet farther from the third nanosheet, and a face of the third nanosheet on a side farther from the first nanosheet is exposed from the first dummy gate interconnect.
9. The semiconductor integrated circuit device of claim 6 , wherein
the second standard cell further includes
a fourth nanosheet extending in the first direction, formed at the same position as the first nanosheet in the first direction, and
a second dummy gate interconnect extending in the second direction, surrounding a periphery of the fourth nanosheet in the second and third directions,
in the third cross section, a face of the third nanosheet on a side opposite to the first side in the second direction is exposed from the first dummy gate interconnect, and
in a fourth cross section cutting the second dummy gate interconnect by a fourth plane defined by the second and third directions along the second direction, a face of the fourth nanosheet on a side opposite to the second side in the second direction is exposed from the second dummy gate interconnect.
10. The semiconductor integrated circuit device of claim 9 , wherein:
the first standard cell further includes
a fifth nanosheet extending in the first direction, formed in the first region, and formed at the same position as the first nanosheet in the first direction, and
a sixth nanosheet extending in the first direction, formed in the second region, and formed at the same position as the first nanosheet in the first direction,
the second standard cell further includes
a seventh nanosheet extending in the first direction, formed at the same position as the first nanosheet in the first direction, and
an eighth nanosheet extending in the first direction, formed at the same position as the first nanosheet in the first direction,
the first gate interconnect surrounds a periphery of the fifth nanosheet in the second and third directions,
the second gate interconnect surrounds a periphery of the sixth nanosheet in the second and third directions,
the first dummy gate interconnect surrounds a periphery of the seventh nanosheet in the second and third directions,
the second dummy gate interconnect surrounds a periphery of the eighth nanosheet in the second and third directions, and
in the first cross section, a face of the fifth nanosheet on a side opposite to the first side in the second direction is exposed from the first gate interconnect,
in the second cross section, a face of the sixth nanosheet on a side opposite to the second side in the second direction is exposed from the second gate interconnect,
in the third cross section, a face of the seventh nanosheet on the first side in the second direction is exposed from the first dummy gate interconnect, and
in the fourth cross section, a face of the eighth nanosheet on the second side in the second direction is exposed from the second dummy gate interconnect.
11. The semiconductor integrated circuit device of claim 6 , wherein
the first and second gate interconnects and the first dummy gate interconnect are formed at the same position in the first direction.