IP Library › Granted Patent US 12,356,843
Granted Patent B2
US 12,356,843 · App. 18/739,262 · Granted Jul 8, 2025

Display apparatus

Inventors: Jinho Kim (Yongin-si, KR); Namhyoung Kim (Yongin-si, KR); Jiyong Jung (Yongin-si, KR)
Assignee: Samsung Display Co., Ltd.
H10K59/88G06F3/0412G06F3/04164G06F3/0446G09G3/006G09G3/3233H10K59/131H10K59/40G09G2300/0819G09G2300/0842G09G2300/0861G09G2330/12G09G2354/00
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Quick Facts
Patent No.
US 12,356,843
App. No.
18/739,262
Granted
Jul 8, 2025
Kind
B2
Abstract

A display apparatus may include a substrate including a display area and a peripheral area, pixel circuits in the display area, data lines in the display area and connected to the pixel circuits, first circuit driving signal lines in the peripheral area, and configured to transmit a first circuit driving signal to drive the pixel circuits, a data test pad portion at the peripheral area, and including data test pads connected to the data lines, a pad portion on the peripheral area, and including first circuit pads connected to the first circuit driving signal lines, a first test pad portion at the peripheral area, and including first circuit test pads connected to the first circuit pads, and a second test pad portion at the peripheral area, and including second circuit test pads connected to the first circuit test pads.

Claims (20)

1. A display apparatus comprising:

a substrate including a display area and a peripheral area surrounding at least a portion of the display area;

a plurality of pixel circuits in the display area;

a plurality of data lines in the display area, extending in a first direction, and electrically connected to the plurality of pixel circuits;

a plurality of gate lines in the display area, extending in a second direction crossing the first direction, and electrically connected to the plurality of pixel circuits;

a gate driver in the peripheral area, and transmitting a gate signal to the plurality of pixel circuits through the plurality of gate lines;

a data test pad portion in the peripheral area, and including a plurality of data test pads electrically connected to the plurality of data lines, respectively;

a pad portion in the peripheral area, and electrically connected to a printed circuit board;

a plurality of output pads in the peripheral area, and connected to the plurality of data lines, respectively;

a first test pad portion in the peripheral area, and spaced apart from the data test pad portion in the first direction; and

a second test pad portion in the peripheral area, and at least partially overlapping the data test pad portion in the first direction.

2. The display apparatus of claim 1 , wherein the plurality of data test pads are connected to the plurality of data lines through the plurality of output pads and a plurality of first connection lines.

3. The display apparatus of claim 2 , wherein each of the plurality of first connection lines connects each of the plurality of data lines to a corresponding one of the plurality of output pads.

4. The display apparatus of claim 1 , wherein the first test pad portion includes a plurality of first circuit test pads,

wherein the second test pad portion includes a plurality of second circuit test pads, and

wherein a size of each of the plurality of first circuit test pads is less than a size of each of the plurality of second circuit test pads.

5. The display apparatus of claim 4 , wherein a size of each of the plurality of second circuit test pads is in a range of 10 times to 15 times a size of each of the plurality of first circuit test pads.

6. The display apparatus of claim 4 , wherein the pad portion includes a plurality of first circuit pads, and

wherein the plurality of first circuit test pads are electrically connected to the plurality of first circuit pads, respectively.

7. The display apparatus of claim 6 , wherein the plurality of second circuit test pads are connected to the gate driver through the plurality of first circuit test pads and the plurality of first circuit pads.

Priority Claims (1)
KR 10-2022-0109267 · Aug 30, 2022 · national
Continuity (2)
Continuation 18310404 · May 1, 2023
Related Publication 20240334800A1 · Oct 3, 2024
References Cited (10)
US 9262953B2 · Jeong et al. · 2016 [cited by applicant]
US 9293425B2 · Lee et al. · 2016 [cited by applicant]
US 10845662B2 · Park et al. · 2020 [cited by applicant]
US 12010901B2 · Kim · 2024 [cited by examiner]
US 20050057273A1 · Lin et al. · 2005 [cited by applicant]
KR 100909417B1 · 2009 [cited by applicant]
KR 1020200017019A · 2020 [cited by applicant]
KR 102172899B1 · 2020 [cited by applicant]
KR 102181165B1 · 2020 [cited by applicant]
KR 102231898B1 · 2021 [cited by applicant]