RRAM bottom electrode
View Patent ↗An integrated circuit device has an RRAM cell that includes a top electrode, an RRAM dielectric layer, and a bottom electrode having a surface that interfaces with the RRAM dielectric layer. Oxides of the bottom electrode are substantially absent from the bottom electrode surface. The bottom electrode has a higher density in a zone adjacent the surface as compared to a bulk region of the bottom electrode. The surface has a roughness Ra of 2 nm or less. A process for forming the surface includes chemical mechanical polishing followed by hydrofluoric acid etching followed by argon ion bombardment. An array of RRAM cells formed by this process is superior in terms of narrow distribution and high separation between low and high resistance states.
1. An integrated circuit device, comprising:
a substrate;
a memory cell formed over the substrate, the memory cell comprising a bottom electrode, a dielectric layer, and a top electrode;
wherein the bottom electrode comprises a bulk region having a composition and an interfacial region that is within the bottom electrode and has the same composition as the bulk region;
the interfacial region forms an interface with the dielectric layer; and
the composition has a higher density within the interfacial region than the composition in the bulk region.
2. The integrated circuit device of claim 1 , wherein:
the composition comprises a first metal; and
the dielectric layer is an oxide of a second metal, which is distinct from the first metal.
3. The integrated circuit device of claim 1 , wherein the interface is free of oxides of the composition.
4. The integrated circuit device of claim 1 , wherein:
the bottom electrode has a surface at the interface; and
the surface has a roughness Ra of 2 nm or less.
5. The integrated circuit device of claim 1 , wherein:
a first portion of the bottom electrode forms a via in a dielectric layer; and
the bulk region is above the via.
6. The integrated circuit device of claim 5 , wherein the bulk region is wider than the via and the interfacial region and the bulk region have equal area.
7. The integrated circuit device of claim 1 , wherein the composition comprises titanium nitride (TiN) or tantalum nitride (TaN).
8. An integrated circuit device, comprising:
a substrate;
an memory cell formed over the substrate, the memory cell comprising a bottom electrode, a data storage layer, and a top electrode;
wherein the bottom electrode comprises a bulk region and an interfacial region, wherein the interfacial region is composed of the same material as the bulk region and is of the same width as the bulk region;
the interfacial region forms an interface with the data storage layer; and
the material has a higher density in the interfacial region than in the bulk region.
9. The integrated circuit device of claim 8 , wherein the interface is free from native oxides of the bottom electrode.
10. The integrated circuit device of claim 8 , wherein the interface has a roughness Ra of 2 nm or less at the interface.
11. The integrated circuit device of claim 8 , wherein the data storage layer is a layer of a metal oxide and the memory cell is an RRAM memory cell.
12. A method, comprising:
providing a semiconductor substrate;
forming a bottom electrode of conductive material over the semiconductor substrate;
performing chemical-mechanical planarization (CMP) on an upper surface of the bottom electrode;
after the CMP, performing a wet etch on the upper surface;
after the wet etch, performing an ion bombardment on the upper surface;
after the ion bombardment, forming a data storage structure on the bottom electrode; and
forming a top electrode of conductive material over the data storage structure.
13. The method of claim 12 , wherein the CMP leaves an oxide of the bottom electrode on the upper surface and the wet etch removes the oxide of the bottom electrode from the upper surface.
14. The method of claim 13 , wherein the ion bombardment takes place before native oxide forms on the upper surface treated by the wet etch.
15. The method of claim 12 , wherein:
the CMP leaves the upper surface with a first roughness; and
the wet etch brings the upper surface to a second roughness, which is greater than the first roughness.
16. The method of claim 15 , wherein the ion bombardment brings the upper surface to a third roughness, which is less than the second roughness.
17. The method of claim 12 , wherein forming the data storage structure on the bottom electrode comprises depositing a metal oxide layer over the bottom electrode.
18. The method of claim 12 , further comprising:
forming a dielectric layer over the semiconductor substrate; and
forming an opening in the dielectric layer;
wherein forming the bottom electrode comprises depositing the conductive material within the opening and also above dielectric layer; and
the bottom electrode interfaces with the data storage structure above the opening.
19. The method of claim 18 , further comprising patterning the bottom electrode, the data storage structure, and the top electrode to form a memory cell having edges, wherein the data storage structure has edges aligned to the edges of the memory cell, and the edges of the data storage structure aligned to the edges of the memory cell are outside the opening.
20. The method of claim 12 , further comprising:
forming a dielectric layer with an opening over the semiconductor substrate; and
patterning the bottom electrode, the data storage structure, and the top electrode to form a memory cell over the opening;
wherein forming the bottom electrode comprises depositing conductive material within the opening;
the opening has a maximum width; and
the data storage structure within the memory cell has a width that is greater than the maximum width of the opening.