Method and apparatus to reduce memory in a NAND flash device to store page related information
The size of page map memory in a NAND flash device used to store page related information is decreased by embedding page type in a row address. The row address is received by the NAND flash device from the host on the data bus in a six-cycle sequence. The received row address is used to decode a physical page address received during the row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array. A same block segment number is used for each page type in the block segment.
1. A non-volatile memory device comprising:
a NAND flash array comprising a plurality of NAND cells arranged in blocks comprising block segments, a given block segment comprising one or more page types; and
control circuitry, the control circuitry to decode a physical page address received during a row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array comprising multiple page types, a same block segment number used for each page type in the block segment.
2. The non-volatile memory device of claim 1 , wherein the word line and the block segment number are stored in a table in a Static Random Access memory.
3. The non-volatile memory device of claim 2 , wherein each block segment has an entry in the table.
4. The non-volatile memory device of claim 1 , wherein the physical page address is received as part of the row address cycle that includes an encoded page type.
5. The non-volatile memory device of claim 4 , wherein the encoded page type is encoded in three bits.
6. The non-volatile memory device of claim 4 , wherein the encoded page type is a static Single Level Cell.
7. The non-volatile memory device of claim 4 , wherein the encoded page type is a dynamic Single Level Cell.
8. The non-volatile memory device of claim 4 , wherein the NAND cells are Quad-Level Cells and the encoded page type is Lower Page, Upper Page, Extra Page or Top Page.
9. The non-volatile memory device of claim 4 , wherein the NAND cells are Penta-Level Cells and the encoded page type is Lower Page, Upper Page, Extra Page, Top Page or Europa Page.
10. The non-volatile memory device of claim 1 , wherein the NAND cells are three Dimensional (3D) NAND cells.
11. A system comprising:
a memory controller; and
a non-volatile memory device, the non-volatile memory device comprising a NAND flash array comprising a plurality of NAND cells arranged in blocks comprising block segments, a given block segment comprising one or more page types; and
control circuitry, the control circuitry to decode a physical page address received during a row address cycle to obtain a word line and a block segment number for a block segment in the word line in the NAND flash array comprising multiple page types, a same block segment number used for each page type in the block segment.
12. The system of claim 11 , wherein the word line and the block segment number are stored in a table in a Static Random Access Memory.
13. The system of claim 12 , wherein each block segment has an entry in the table.
14. The system of claim 11 , wherein the physical page address is received as part of the row address cycle that includes an encoded page type.
15. The system of claim 14 , wherein the encoded page type is encoded in three bits.
16. The system of claim 14 , wherein the encoded page type is a static Single Level Cell.
17. The system of claim 14 , wherein the encoded page type is a dynamic Single Level Cell.
18. The system of claim 14 , wherein the NAND cells are Penta-level Cells and the encoded page type is Lower Page, Upper Page, Extra Page, Top Page or Europa Page.
19. The system of claim 11 , wherein the NAND cells are three Dimensional (3D) NAND cells.
20. The system of claim 11 , further comprising:
one or more of:
a processor,
a power supply, and
a display coupled with the non-volatile memory device.