Memory device, integrated circuit device and method
A memory device includes a bit line, a word line, a memory cell including a capacitor and a transistor, and a controller. The transistor has a gate terminal coupled to the word line, a first terminal, and a second terminal. The capacitor has a first end coupled to the first terminal of the transistor, a second end coupled to the bit line, and an insulating material between the first end and the second end. The controller, in a programming operation, applies a turn-ON voltage via the word line to the gate terminal of the transistor to turn ON the transistor, and applies a program voltage via the bit line to the second end of the capacitor to apply, while the transistor is turned ON, a predetermined break-down voltage or higher between the first end and the second end of the capacitor to break down the insulating material of the capacitor.
1. A memory device, comprising:
at least one bit line;
at least one word line;
at least one memory cell comprising a capacitor and a transistor; and
a controller coupled to the at least one memory cell via the at least one bit line and the at least one word line,
wherein
the transistor has
a gate terminal coupled to the word line,
a first terminal, and
a second terminal,
the capacitor has
a first end coupled to the first terminal of the transistor,
a second end coupled to the bit line, and
an insulating material between the first end and the second end, and configured to break down under a predetermined break-down voltage or higher applied between the first end and the second end,
the controller is configured to, in a programming operation,
apply a turn-ON voltage via the at least one word line to the gate terminal of the transistor to turn ON the transistor, and
apply a program voltage via the at least one bit line to the second end of the capacitor to apply, while the transistor is turned ON, the predetermined break-down voltage or higher between the first end and the second end of the capacitor to break down the insulating material of the capacitor to write into the at least one memory cell a first logic value corresponding to the insulating material that has been broken down.
2. The memory device of claim 1 , wherein
the memory device further comprises at least one further memory cell storing a second logic value different from the first logic value, the second logic value corresponding to an insulating material of the at least one further memory cell not yet broken down.
3. The memory device of claim 1 , wherein
the second terminal of the transistor is grounded.
4. The memory device of claim 1 , wherein
the controller is configured to, in a read operation,
apply the turn-ON voltage via the at least one word line to the gate terminal of the transistor to turn ON the transistor, and
apply a read voltage via the at least one bit line to the second end of the capacitor to detect, while the transistor is turned ON, a datum stored in the at least one memory cell.
5. The memory device of claim 1 , wherein
the at least one word line is a plurality of word lines,
the at least one memory cell is a plurality of memory cells,
the second ends of the capacitors of the plurality of memory cells are commonly coupled to the at least one bit line,
the gate terminals of the transistors of the plurality of memory cells are correspondingly coupled to the plurality of word lines, and
the second terminals of the transistors of the plurality of memory cells are grounded.
6. The memory device of claim 1 , wherein
the at least one bit line is a plurality of bit lines,
the at least one word line is a plurality of word lines,
the at least one memory cell is a plurality of strings of memory cells,
the second ends of the capacitors of the memory cells in each string among the plurality of strings of memory cells are commonly coupled to a corresponding bit line among the plurality of bit lines,
the gate terminals of the transistors of the memory cells in each string among the plurality of strings of memory cells are correspondingly coupled to the plurality of word lines, and
the second terminals of the transistors of the memory cells in the plurality of strings of memory cells are grounded.
7. The memory device of claim 1 , further comprising:
a substrate having thereon the transistor; and
at least one metal layer over the substrate, the at least one metal layer comprising the at least one bit line, and
a conductive pattern electrically isolated from the at least one bit line.
8. The memory device of claim 7 , wherein
the first end of the capacitor is electrically coupled to a first portion of the conductive pattern,
the second end of the capacitor is electrically coupled to the at least one bit line, and
a second portion of the conductive pattern is electrically coupled to the first terminal of the transistor.
9. The memory device of claim 8 , wherein
the at least one metal layer is higher than a metal-zero layer over the substrate.
10. The memory device of claim 1 , wherein
the capacitor is a metal-insulator-metal (MIM) capacitor.
11. An integrated circuit (IC) device, comprising:
a substrate having thereon a plurality of transistors;
a metal layer over the substrate, the metal layer comprising:
at least one bit line, and
a plurality of conductive patterns electrically isolated from the at least one bit line; and
a plurality of metal-insulator-metal (MIM) structures between the metal layer and the substrate in a thickness direction of the substrate,
wherein
each MIM structure among the plurality of MIM structures comprises:
a first conductive pattern in a first conductive layer over the substrate, the first conductive pattern electrically coupled to the at least one bit line,
a second conductive pattern in a second conductive layer over the substrate, the second conductive pattern electrically coupled to a corresponding conductive pattern among the plurality of conductive patterns, the corresponding conductive pattern electrically coupled to a first source/drain region of a corresponding transistor among the plurality of transistors, and
an insulating material in an insulating layer between the first conductive layer and the second conductive layer.
12. The IC device of claim 11 , wherein
the first conductive layer is between the metal layer and the substrate in the thickness direction, and
the second conductive layer is between the metal layer and the substrate in the thickness direction.
13. The IC device of claim 12 , further comprising:
a plurality of first vias, a plurality of second vias, and a plurality of third vias,
wherein, for each MIM structure among the plurality of MIM structures,
a first via among the plurality of first vias extends downward in the thickness direction from the at least one bit line to the first conductive pattern of the MIM structure,
a second via among the plurality of second vias extends downward in the thickness direction from a first portion of the corresponding conductive pattern to the second conductive pattern of the MIM structure, and
a third via among the plurality of third vias extends downward in the thickness direction from a second portion of the corresponding conductive pattern to electrically couple the second conductive pattern of the MIM structure to the first source/drain region of the corresponding transistor.
14. The IC device of claim 13 , wherein
each MIM structure among the plurality of MIM structures does not overlap the corresponding transistor in the thickness direction of the substrate.
15. The IC device of claim 12 , further comprising:
first and second passivation layers between which the first conductive layer, the second conductive layer and the insulating layer are sandwiched in the thickness direction.
16. The IC device of claim 11 , wherein
each transistor among the plurality of transistors further comprises a second source/drain region which is grounded.
17. The IC device of claim 11 , further comprising:
a plurality of word lines each electrically coupled to a gate region of a corresponding transistor among the plurality of transistors.
18. The IC device of claim 11 , further comprising:
an interconnect structure over the substrate and electrically coupled to the plurality of transistors,
wherein
the interconnect structure comprises a plurality of metal layers stacked one over another in the thickness direction,
the plurality of metal layers comprises
the metal layer comprising the at least one bit line, and
a underlying metal layer immediately below the metal layer, and
each of the plurality of MIM structures is entirely between the metal layer and the underlying metal layer in the thickness direction.
19. A method, comprising:
forming a plurality of transistors over a substrate;
forming a plurality of metal-insulator-metal (MIM) structures over the plurality of transistors, wherein
each MIM structure among the plurality of MIM structures comprises:
a first conductive pattern in a first conductive layer over the substrate,
a second conductive pattern in a second conductive layer over the substrate, and
an insulating material in an insulating layer between the first conductive layer and the second conductive layer;
forming a plurality of first vias, a plurality of second vias, and a plurality of third vias, wherein, for each MIM structure among the plurality of MIM structures,
the first conductive pattern is under and in electrical contact with a lower end of a corresponding first via among the plurality of first vias,
the second conductive pattern is under and in electrical contact with a lower end of a corresponding second via among the plurality of second vias, and
a source/drain region of a corresponding transistor among the plurality of transistors is electrically coupled to a lower end of a corresponding third via among the plurality of third vias;
forming a plurality of conductive patterns over the plurality of MIM structures, wherein
each conductive pattern among the plurality of conductive patterns is over and electrically couples an upper end of a second via among the plurality of second vias and an upper end of a third via among the plurality of third vias, to electrically couple the second conductive pattern of each MIM structure among the plurality of MIM structures to the source/drain region of the corresponding transistor; and
forming a plurality of bit lines over the plurality of MIM structures, wherein
each bit line among the plurality of bit lines is over and in electrical contact with upper ends of the first vias electrically coupled to the first conductive patterns of multiple MIM structures among the plurality of MIM structures.
20. The method of claim 19 , further comprising:
forming a plurality of word lines over the plurality of transistors, wherein
the plurality of transistors is arranged in an array comprising rows and columns transverse to the rows,
the transistors in each of the columns comprise:
first transistors having gates electrically coupled to a first corresponding word line among the plurality of word lines, and
second transistors having gates electrically coupled to a second corresponding word line among the plurality of word lines, and
each bit line among the plurality of bit lines is electrically coupled to the first conductive patterns of the MIM structures in two of the rows.