Analog neuromorphic circuit implemented using resistive memories
An analog neuromorphic circuit is disclosed, having input voltages applied to a plurality of inputs of the analog neuromorphic circuit. The circuit also includes a plurality of resistive memories that provide a resistance to each input voltage applied to each of the inputs so that each input voltage is multiplied in parallel by the corresponding resistance of each corresponding resistive memory to generate a corresponding current for each input voltage and each corresponding current is added in parallel. The circuit also includes at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel. The multiplying of each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
1. An analog neuromorphic system that implements a plurality of resistive memories, comprising:
a first plurality of wires positioned to intersect a second plurality of wires forming a first wire grid;
a first plurality of resistive memories with each resistive memory positioned at an intersection of the first plurality of wires and the second plurality of wires and configured to provide a resistance to each input voltage applied to each of the first plurality of wires so that each input voltage of the first wire grid is multiplied in parallel by the corresponding resistance to generate a corresponding current for each input voltage and each corresponding current is added in parallel; and
at least one output signal that is generated from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel, wherein multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
2. The analog neuromorphic system of claim 1 , further comprising:
a first plurality of comparators with each comparator coupled to a pair of wires from the second plurality of wires at a first input and a second input of each component and configured to:
compare a magnitude of each voltage that is associated with each respective current conducted by each respective pair or wires from the second plurality of vertical wires that are coupled to each respective first input and second input of each respective comparator, and
generate an output signal that is representative of how the magnitude of each voltage associated with each respective current is compared to each other voltage associated with each respective current that is conducted by each respective pair of wires from the second plurality of vertical wires that are coupled to each respective first input and second input of each respective comparator.
3. The analog neuromorphic system of claim 2 , further comprising:
a third plurality of wires positioned to intersect with a fourth plurality of wires forming a second wire grid, wherein each wire from the plurality of wires is coupled to a respective output of each comparator from the first plurality of comparators;
a second plurality of resistive memories with each resistive memory positioned at an intersection of the third plurality of wires and the fourth plurality of wires and configured to:
provide a resistance to each input voltage applied to each wire of the third plurality of wires so that each input voltage of the second wire grid is multiplied by the corresponding resistance in addition to the multiplication of each input voltage with the corresponding resistance of the first wire grid,
add each current of the second wire grid to generate a plurality of accumulative currents with each accumulative current being conducted by each corresponding wire of the fourth plurality of wires in addition to the adding of the first wire grid; and
a second plurality of comparators with each comparator coupled to a pair of wires from the fourth plurality of wires at a first input and a second input of each comparator from the second plurality of comparators and configured to:
compare a magnitude of each voltage associated with each respective accumulative current conducted by each respective pair of wires from the fourth plurality of wires that are coupled to each respective first input and second input of each respective comparator from the second plurality of comparators, and
generate an output signal that is representative of how the magnitude of each voltage associated with each respective accumulated current is compared to each other voltage associated with each respective accumulated current that is conducted by each respective pair of wires from the fourth plurality of wires that are coupled to each respective input and second input of each respective comparator from the second plurality of comparators.
4. The analog neuromorphic system of claim 3 , wherein each input voltage applied to each wire of the first plurality of wires drives both the first wire grid and the first plurality of comparators forming a first layer of neurons of a neural network and the output of each comparator from the first plurality of comparators drives both the second wire gird and the second plurality of comparators forming a second layer of neurons from the neural network.
5. The analog neuromorphic system of claim 4 , wherein each resistance provided by each resistive memory associated with the first layer of neurons is weighted to determine a functionality of the first layer of neurons and each resistance provided by each resistive memory associated with the second layer of neurons is weighted to determine a functionality of the second layer of neurons.
6. The analog neuromorphic system of claim 5 , wherein each resistance provided by a pair of resistive memories generates a single weight for the pair of resistive memories, wherein each pair of resistive memories includes two resistive memories that are positioned on a same wire from the first plurality of wires and/or the third plurality of wires and a same pair of wires from the second plurality of wires and/or the fourth plurality of wires that are coupled to a first output and a second output of a same comparator.
7. A method for generating computation operations in parallel by implementing a plurality of resistive memories, comprising:
positioning a first plurality of wires to intersect with a second plurality of wires forming a first wire grid;
providing, by a first plurality of resistive memories with each resistive memory positioned at an intersection of the first plurality of wires and the second plurality of wires, a resistance to each input voltage applied to each of the first plurality of wires so that each input voltage of the first wire grid is multiplied in parallel by the corresponding resistance to generate a corresponding current for each input voltage and each corresponding current is added in parallel; and
generating at least one output signal from each of the input voltages multiplied in parallel with each of the corresponding currents for each of the input voltages added in parallel, wherein multiplying each input voltage with each corresponding resistance is executed simultaneously with adding each corresponding current for each input voltage.
8. The method of claim 7 , further comprising:
comparing, by a first plurality of comparators with each comparator coupled to a pair of wires from the second plurality of wires at a first input and a second input of each comparator, a magnitude of each voltage that is associated with each respective current conducted by each respective pair of wires from the second plurality of vertical wires that are coupled to each respective first input and second input of each respective comparator; and
generating an output signal that is representative of how the magnitude of each voltage associated with each respective current is compared to each other voltage associated with each respective current that is conducted by each respective pair of wires from the second plurality of vertical wires that are coupled to each respective first input and second input of each respective comparator.
9. The method of claim 8 , further comprising:
positioning a third plurality of wires to intersect with a fourth plurality of wires forming a second wire grid, wherein each wire from the third plurality of wires is coupled to a respective output of each comparator from the first plurality of comparators;
providing, by a second plurality of resistive memories with each resistive memory positioned at an intersection of the third plurality of wires and the fourth plurality of wires, a resistance to each input voltage applied to each wire of the third plurality of wires so that each input voltage of the second wire grid is multiplied by the corresponding resistance in addition to the multiplication of each input voltage with the corresponding resistance of the first wire grid;
adding each current of the second wire grid to generate a plurality of accumulative currents with each accumulative current being conducted by each corresponding wire of the fourth plurality of wires in addition to the adding of the first wire grid;
comparing, by a second plurality of comparators with each comparator coupled to a pair of wires from the fourth plurality of wires at a first input and a second input of each comparator from the second plurality of comparators, a magnitude of each voltage associated with each respective accumulative current conducted by each respective pair of wires from the fourth plurality of wires that are coupled to each respective input and second input of each respective comparator from the second plurality of comparators; and
generating an output signal that is representative of how the magnitude of each voltage associated with each respective accumulated current is compared to each other voltage associated with each respective accumulated current that is conducted by each respective pair of wires from the fourth plurality of wires that are coupled to each respective input and second input of each respective comparator from the second plurality of comparators.
10. The method of claim 9 , further comprising:
driving, by each input voltage applied to each wire of the first plurality of wires, both the first wire grid and the first plurality of comparators forming a first layer of neurons of a neural network; and
driving, by the output of each comparator from the first plurality of comparators, both the second wire grid and the second plurality of comparators forming a second layer of neurons of the neural network.
11. The method of claim 10 , further comprising:
weighting each resistance provided by each resistive memory associated with the first layer of neurons is weighted to determine a functionality of the first layer of neurons; and
weighting each resistance provided by each resistive memory associated with the second layer of neurons to determine a functionality of the second layer of neurons.
12. The method of claim 11 , further comprising:
generating, by each resistance provided by a pair of resistive memories, a single weight for the pair of resistive memories, wherein each pair of resistive memories includes two resistive memories that are positioned on a same wire from the first plurality of wires and/or the third plurality of wires and a same pair of wires from the second plurality of wires and/or the fourth plurality of wires that are coupled to a first output and a second output of a same comparator.