In-memory computing (IMC) memory device and in-memory computing method

1. An in-memory computing (IMC) memory device, comprising:

a plurality of computing memory cells, the plurality of computing memory cells forming a plurality of memory strings, the plurality of computing memory cells storing a plurality of weight values;

a loading capacitor coupled to the plurality of computing memory cells; and

a measurement circuit coupled to the loading capacitor,

wherein in a plurality of IMC operations performed by the IMC memory device,

a plurality of input voltages are input into the plurality of computing memory cells, the plurality of input voltages being corresponding to a plurality of input values,

a plurality of effective resistances of the computing memory cells are corresponding to the input voltages and the weight values,

when a read voltage is applied to the plurality of computing memory cells, the plurality of computing memory cells are configured to generate a plurality of cell currents, the plurality of cell currents are summed into a plurality of memory string currents,

the plurality of memory strings are configured to charge the loading capacitor with the plurality of memory string currents,

the measurement circuit is configured to measure a capacitor voltage of the loading capacitor, and

based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage, an operation result of the plurality of input values and the plurality of weight values is determined.

2. The IMC memory device according to claim 1 , wherein

each of the plurality of memory strings are coupled in parallel, and each of the plurality of memory strings includes at least two cascaded memory cells, and

the delay time is defined as from a first timing when the read voltage is applied until a second timing when the capacitor voltage of the loading capacitor is charged to the predetermined voltage, the predetermined voltage is determined based on the read voltage.

3. The IMC memory device according to claim 1 , wherein at a plurality of predetermined delay times, whether the capacitor voltage reaches the predetermined voltage is checked to generate a comparison result, the comparison result indicating the operation result of the input values and the weight values.

4. The IMC memory device according to claim 1 , wherein each of the plurality of computing memory cells includes:

a transistor, coupled to a bit line, wherein the transistor receives the read voltage through the bit line and receives the input voltage for generating the cell current,

a threshold voltage of the transistor is adjusted as a first threshold voltage value or a second threshold voltage value in response to the weight value; and

in response to the input voltage and the threshold voltage of the transistor, the transistor is in a turned-on state or a turned-off state.

5. The IMC memory device according to claim 4 , wherein:

when the input voltage has a first input voltage value and the threshold voltage has the second threshold voltage value, the transistor is in the turned-off state, the computing memory cell generates no cell current; and

when the input voltage has a second input voltage value, the transistor is in the turned-on state, the computing memory cell generates the cell current;

the first input voltage value is lower than the second input voltage value, the first threshold voltage value is lower than the second threshold voltage value, the first input voltage value is lower than the second threshold voltage value, and the first voltage difference is lower than the second voltage difference.

6. The IMC memory device according to claim 5 , wherein each of the plurality of computing memory cells further comprises:

a resistor, coupled to the transistor in parallel and coupled to the bit line, the resistor has a fixed resistance value or a variable resistance value,

the variable resistance value of the resistor is adjusted as at least a first resistance value or a second resistance value in response to the weight value.

7. The IMC memory device according to claim 1 , wherein each of the plurality of computing memory cells includes:

a multiplexer; and

a plurality of resistors coupled to the multiplexer,

wherein

the multiplexer receives the read voltage and the input voltage,

based on the input value, the multiplexer applies the read voltage to one of the plurality of resistors,

the cell current generated by the computing memory cell is corresponding to the read voltage and one of the plurality of resistors, and

based on the weight value of the computing memory cell, resistance values of the plurality of resistors are adjusted.

8. The IMC memory device according to claim 1 , wherein each of the plurality of computing memory cells includes:

a plurality of switches receiving the input voltage; and

a plurality of resistors coupled to the plurality of switches,

wherein

the input voltage controls turning on or off of the plurality of switches and thus the rad voltage is selectively applied to one of the plurality of resistors via the plurality of switches, and

based on the weight value of the computing memory cell, resistance values of the plurality of resistors are adjusted.

9. The IMC memory device according to claim 1 , further including:

a plurality of resistance elements included in the plurality of memory strings, the plurality of resistance elements being serially coupled to the plurality of computing memory cells.

10. The IMC memory device according to claim 9 , wherein

the plurality of computing memory cells have a first resistance value and a second resistance value lower than the first resistance value; and

an equivalent resistance of the plurality of computing memory cells is equivalent to or higher than double of the second resistance value, or the equivalent resistance of the plurality of computing memory cells is equivalent to or higher than a half of the first resistance value.

11. An in-memory computing (IMC) method applicable to an IMC memory device, the IMC method comprising:

storing a plurality of weight values in a plurality of computing memory cells, the plurality of computing memory cells forming a plurality of memory strings;

inputting a plurality of input voltages into the plurality of computing memory cells, the plurality of computing memory cells having a plurality of effective resistances corresponding to the input voltages and the weight values, the plurality of input voltages being corresponding to a plurality of input values;

generating, when a read voltage is applied to the plurality of computing memory cells, a plurality of cell currents from the plurality of computing memory cells, the plurality of cell currents are summed into a plurality of memory string currents;

charging the loading capacitor with the plurality of memory string currents from the plurality of memory strings;

measuring a capacitor voltage of the loading capacitor; and

determining an operation result of the plurality of input values and the plurality of weight values based a relationship between the capacitor voltage of the loading capacitor, at least one delay time and a predetermined voltage.

12. The IMC method according to claim 11 , wherein the delay time is defined as from a first timing when the read voltage is applied until a second timing when the capacitor voltage of the loading capacitor is charged to the predetermined voltage, the predetermined voltage determined based on the read voltage.

13. The IMC method according to claim 11 , wherein at a plurality of predetermined delay times, whether the capacitor voltage reaches the predetermined voltage is checked to generate a comparison result, the comparison result indicating the operation result of the input values and the weight values.

14. The IMC method according to claim 11 , wherein each of the plurality of computing memory cells includes:

a transistor, coupled to a bit line,

wherein

the transistor receives the read voltage through the bit line and receives the input voltage, and the computing memory cell generates the cell current;

a threshold voltage of the transistor is adjusted as a first threshold voltage value or a second threshold voltage value in response to the weight value; and

in response to the input voltage and the threshold voltage of the transistor, the transistor is in a turned-on state or a turned-off state.

15. The IMC method according to claim 14 , wherein:

when the input voltage has a first input voltage value and the threshold voltage has the second threshold voltage value, the transistor is in the turned-off state, the computing memory cell generates no cell current; and

when the input voltage has a second input voltage value, the transistor is in the turned-on state, the computing memory cell generates the cell current;

the first input voltage value is lower than the second input voltage value, the first threshold voltage value is lower than the second threshold voltage value, the first input voltage value is lower than the second threshold voltage value, and the first voltage difference is lower than the second voltage difference.

16. The IMC method according to claim 15 , wherein each of the plurality of computing memory cells further comprises:

a resistor, coupled to the transistor in parallel and coupled to the bit line,

wherein

the resistor has a fixed resistance value or a variable resistance value,

the variable resistance value of the resistor is adjusted as at least a first resistance value or a second resistance value in response to the weight value.

17. The IMC method according to claim 11 , wherein each of the plurality of computing memory cells includes:

a multiplexer; and

a plurality of resistors coupled to the multiplexer,

wherein

the multiplexer receives the read voltage and the input voltage,

based on the input value, the multiplexer applies the read voltage to one of the plurality of resistors,

the cell current generated by the computing memory cell is corresponding to the read voltage and one of the plurality of resistors, and

based on the weight value of the computing memory cell, resistance values of the plurality of resistors are adjusted.

18. The IMC method according to claim 11 , wherein each of the plurality of computing memory cells includes:

a plurality of switches receiving the input voltage; and

a plurality of resistors coupled to the plurality of switches,

wherein

the input voltage controls turning on or off of the plurality of switches and thus the rad voltage is selectively applied to one of the plurality of resistors via the plurality of switches, and

based on the weight value of the computing memory cell, resistance values of the plurality of resistors are adjusted.

19. The IMC method according to claim 11 , wherein:

the IMC memory device further includes a plurality of resistance elements included in the plurality of memory strings, the plurality of resistance elements being serially coupled to the plurality of computing memory cells;

the plurality of computing memory cells have a first resistance value and a second resistance value lower than the first resistance value; and

an equivalent resistance of the plurality of computing memory cells is equivalent to or higher than double of the second resistance value, or the equivalent resistance of the plurality of computing memory cells is equivalent to or higher than a half of the first resistance value.