Method of manufacturing semiconductor devices

1. A method of manufacturing a semiconductor device, comprising:

forming a target layer to be patterned over a substrate;

forming a mask layer having an opening over the target layer;

enlarging the opening in a first direction without enlarging the opening in a second direction crossing the first direction by a directional process, the first and second directions being parallel to an upper surface of the substrate; and

patterning the target layer to form a hole pattern corresponding to the opening.

2. The method of claim 1 , wherein the opening is shrunk in the second direction during the directional process.

3. The method of claim 2 , wherein an enlarging amount of the opening in the first direction is greater than a shrinkage amount of the opening in the second direction.

4. The method of claim 2 , wherein an enlarging amount of the opening in the first direction is twice time or more a shrinkage amount of the opening along the second direction.

5. The method of claim 1 , wherein the mask layer is made of an oxide.

6. The method of claim 5 , wherein the oxide is silicon oxide and the target layer is made of a material different from the silicon oxide.

7. The method of claim 1 , wherein:

the directional process comprises applying Ar ions towards an upper surface of the mask layer at an angle θ, which is an angle between an ion beam direction and the upper surface, and

the angle θ is more than zero degrees and equal to or less than 45 degrees.

8. The method of claim 1 , wherein:

the directional process comprises applying radicals generated by a plasma towards an upper surface of the mask layer at an angle θ, which is an angle between a radial beam direction and the upper surface, and

the angle θ is more than zero degrees and equal to or less than 45 degrees.

9. A method of manufacturing a semiconductor device, comprising:

forming a lower conductive wire extending in a first direction over a substrate;

forming an interlayer dielectric (ILD) layer over the lower conductive wire;

forming a mask layer including an opening over the ILD layer;

enlarging the opening in the first direction and shrinking the opening in a second direction crossing the first direction by a directional process, the first and second directions being parallel to an upper surface of the substrate;

patterning the ILD layer to form a via hole corresponding to the opening; and

forming a via contact by filling a conductive material into the via hole.

10. The method of claim 9 , wherein the mask pattern includes an upper oxide layer as an uppermost layer.

11. The method of claim 10 , wherein:

the mask pattern further includes a first middle layer and a bottom oxide layer, and

a bottom of the opening is located at a middle of the bottom oxide layer.

12. The method of claim 10 , wherein:

a bottom layer is formed between the ILD layer and the bottom oxide layer, and

the patterning the ILD layer comprises:

patterning a remaining part of the bottom oxide layer to expose the bottom layer, wherein the upper oxide layer is removed during the patterning the remaining part of the bottom oxide layer;

patterning the bottom layer by using the middle layer and the bottom oxide layer as an etching mask; and

patterning the ILD layer by using the bottom layer as an etching mask.

13. The method of claim 10 , wherein the upper oxide layer includes one of a silicon oxide, a silicon oxide containing nitrogen, an aluminum oxide or a hafnium oxide.

14. The method of claim 9 , wherein:

the directional process comprises applying ions of Ar, N or Si towards an upper surface of the mask layer at an angle θ, which is an angle between an ion beam direction and the upper surface, and

the angle θ is more than zero degrees and equal to or less than 45 degrees.

15. The method of claim 9 , wherein:

the directional process comprises applying radicals generated by a plasma towards an upper surface of the mask layer at an angle θ, which is an angle between a radial beam direction and the upper surface, and

the angle θ is more than zero degrees and equal to or less than 45 degrees.

16. A method of manufacturing a semiconductor device, comprising:

forming a lower conductive wire extending in a first direction over a substrate;

forming an interlayer dielectric (ILD) layer over the lower conductive wire;

forming a first bottom layer over the ILD layer;

forming a mask layer including a first mask layer over the first bottom layer, a second mask layer over the first mask layer and a third mask layer over the second mask layer;

forming a second bottom layer over the mask layer;

forming a middle layer over the second bottom layer;

forming a photo resist pattern having an opening over the middle layer;

etching the middle layer by using the photo resist pattern as an etching mask;

etching the second bottom layer by using at least one of the middle layer or the photo resist pattern as an etching mask;

forming an opening corresponding to the opening by etching the third mask layer and the second mask layer by using the second bottom layer as an etching mask;

removing the second bottom layer;

enlarging the opening in the first direction without enlarging the opening in a second direction crossing the first direction by a directional process, the first and second directions being parallel to an upper surface of the substrate;

etching the first mask layer;

etching the first bottom layer;

patterning the ILD layer to form a via hole corresponding to the opening; and

forming a via contact by filling a conductive material into the via hole.

17. The method of claim 16 , wherein the third mask layer includes a silicon oxide.

18. The method of claim 17 , wherein the opening is shrunk in the second direction during the directional process.

19. The method of claim 18 , wherein the second mask layer includes SiC.

20. The method of claim 19 , wherein the first mask layer includes a silicon oxide.