Method of manufacturing semiconductor devices
In a method of forming a pattern, a first pattern is formed over an underlying layer, the first pattern including main patterns and a lateral protrusion having a thickness of less than 25% of a thickness of the main patterns, a hard mask layer is formed over the first pattern, a planarization operation is performed to expose the first pattern without exposing the lateral protrusion, a hard mask pattern is formed by removing the first pattern while the lateral protrusion being covered by the hard mask layer, and the underlying layer is patterned using the hard mask pattern as an etching mask.
1. A method of manufacturing a semiconductor device, comprising:
forming a first hard mask layer over a target layer to be patterned;
forming a photo resist layer over the first hard mask layer;
patterning the photo resist layer;
etching the first hard mask layer using the patterned photo resist layer as an etching mask to form first etched portions of the first hard mask layer;
forming a second hard mask layer over the patterned photo resist layer and the first hard mask layer,
wherein the second hard mask layer fills the first etched portions of the first hard mask layer;
planarizing the second hard mask layer to expose an upper surface of the first hard mask layer and form a second hard mask layer pattern; and
etching exposed portions of the first hard mask layer and the target layer using the second hard mask layer pattern as an etching mask.
2. The method according to claim 1 , wherein the first hard mask layer and the second hard mask layer are made of different materials.
3. The method according to claim 2 , wherein the first hard mask layer and the second hard mask layer include a dielectric material.
4. The method according to claim 3 , wherein the first hard mask layer and the second hard mask layer include silicon oxide, silicon nitride, SiOC, SiOCN, SiCN, aluminum oxide, aluminum nitride, aluminum oxynitride, hafnium oxide, titanium oxide, or zirconium oxide.
5. The method according to claim 2 , wherein the first hard mask layer and the second hard mask layer include amorphous silicon, polycrystalline silicon, TiN, or TaN.
6. The method according to claim 2 , wherein the second hard mask layer has a higher etching selectivity with respect to the first hard mask layer.
7. The method according to claim 1 , wherein the first hard mask layer has a higher etching selectivity with respect to the target layer.
8. The method according to claim 1 , wherein a depth of the first etched portions of the first hard mask layer ranges from 25% to less than 100% of a thickness of the first hard mask layer.
9. A method of manufacturing a semiconductor device, comprising:
patterning a photo resist layer to form photo resist pattern over an underlying layer,
wherein the photo resist pattern includes resist scum between adjacent photo resist pattern features;
forming a hard mask layer over the photo resist pattern,
wherein the hard mask layer includes a seam or void extending along a first direction between the adjacent photo resist pattern features of the photo resist pattern and a recess located at an end of the seam or void along the first direction,
wherein the recess is located at a greater distance from the underlying layer along the first direction than an uppermost surface of the photo resist pattern;
exposing an upper portion of the photo resist pattern;
forming a hard mask pattern by etching exposed portions of the photo resist pattern using the hard mask pattern as an etching mask; and
patterning the underlying layer using the hard mask pattern as an etching mask.
10. The method according to claim 9 , wherein the hard mask layer is made of a dielectric material selected from the group consisting of silicon nitride, SiON, SiOC, SiOCN, SiCN, aluminum oxide, aluminum nitride, aluminum oxynitride, hafnium oxide and zirconium oxide.
11. The method according to claim 9 , wherein the photo resist pattern includes a plurality of line patterns extending in a first direction and arranged parallel to each other in a second direction crossing the first direction.
12. The method according to claim 11 , wherein the hard mask pattern includes a plurality of line patterns extending in the first direction and disposed at positions where a plurality of spaces of the photo resist pattern are located.
13. The method of claim 9 , wherein the underlying layer is made of a conductive material and the hard mask pattern is made of a dielectric material.
14. The method of claim 9 , wherein the underlying layer is made of a dielectric material and the hard mask pattern is made of a dielectric material different from the underlying layer.
15. The method of claim 9 , wherein the underlying layer includes an organic material.
16. A method of manufacturing a semiconductor device, comprising:
forming a photo resist layer over an underlying layer disposed over a semiconductor substrate;
determining an optimum dose amount of actinic radiation to form a pattern in the photo resist layer exposing the underlying layer;
selectively exposing the photo resist layer to an exposure dose amount of actinic less than the optimum dose amount,
wherein the exposure dose amount is 10% to 40% less than the optimum dose amount;
developing the exposed photo resist layer to form a photo resist pattern;
forming a hard mask layer over the photo resist pattern;
removing a portion of the hard mask layer to expose an upper portion of the photo resist pattern;
forming a hard mask pattern by removing the photo resist pattern; and
etching the underlying layer by using the hard mask pattern as an etching mask.
17. The method of claim 16 , wherein the photo resist pattern includes resist scum between adjacent photo resist pattern features.
18. The method of claim 17 , wherein the hard mask pattern covers the resist scum.
19. The method of claim 17 , wherein a seam or a void is formed in the hard mask layer extending in a first direction between the adjacent photo resist pattern features.
20. The method of claim 19 , wherein a recess is formed at an end of the seam or void along the first direction, and the recess is located at a greater distance from the underlying layer along the first direction than an uppermost surface of the photo resist pattern.