Self aligned contact scheme
View Patent ↗A method includes using a second hard mask layer over a gate stack to protect the gate electrode during etching a self-aligned contact. The second hard mask is formed over a first hard mask layer, where the first hard mask layer has a lower etch selectivity than the second hard mask layer.
1. A device comprising:
a gate structure comprising a gate dielectric, a gate electrode, and a first gate spacer and a second gate spacer disposed on opposing sides of the gate electrode;
a first hard mask layer over the gate electrode and the gate dielectric;
a second hard mask layer disposed over the first gate spacer, the second hard mask layer being a different material than a material of the first hard mask layer, the second hard mask layer and the first hard mask layer contacting the first gate spacer; and
a conductive feature adjacent the first gate spacer.
2. The device of claim 1 , wherein the second hard mask layer contacts a sidewall of the first hard mask layer.
3. The device of claim 1 , wherein the first gate spacer contacts a sidewall of the first hard mask layer.
4. The device of claim 1 , wherein an upper surface of the second hard mask layer has a recess.
5. The device of claim 4 , wherein the conductive feature extends into the recess.
6. The device of claim 1 , wherein an upper surface of the first hard mask layer is free of the second hard mask layer.
7. The device of claim 1 , further comprising:
a third hard mask layer disposed over the second gate spacer, the third hard mask layer being a same material as the second hard mask layer, the third hard mask layer and the first hard mask layer contacting the second gate spacer.
8. The device of claim 7 , wherein the third hard mask layer is discontinuous from the second hard mask layer.
9. A device comprising:
a gate structure, wherein the gate structure comprises a gate electrode over a gate dielectric, and a first gate spacer and a second gate spacer disposed on either side of the gate electrode;
a first source/drain and a second source/drain on opposing sides of the gate structure;
a first etch stop layer on a sidewall of the gate structure;
a first hard mask over the gate electrode; and
a second hard mask over the first etch stop layer.
10. The device of claim 9 , wherein the second hard mask is in contact with a sidewall of the first hard mask.
11. The device of claim 9 , wherein the second hard mask contacts the first gate spacer.
12. The device of claim 9 , wherein the second hard mask is spaced apart from the gate electrode.
13. The device of claim 9 , further comprising:
a conductive feature directly contacting the first source/drain and the second hard mask.
14. The device of claim 9 , wherein an upper surface of the first hard mask is level with an upper surface of the second hard mask.
15. A device comprising:
a gate structure over a channel region, the gate structure comprising a gate electrode, a gate mask over the gate electrode, and a first gate spacer and a second gate spacer on opposing sides of the gate electrode, and
a first source/drain and a second source/drain on opposing sides of the gate structure;
a first dielectric layer over a sidewall of the first gate spacer and on an upper surface of the first source/drain, the first gate spacer being between the first dielectric layer and the gate electrode;
a second dielectric layer over a sidewall of the second gate spacer and on an upper surface of the second source/drain, the second gate spacer being between the second dielectric layer and the gate electrode;
a third dielectric layer adjacent the second dielectric layer, the second dielectric layer being between the third dielectric layer and the second gate spacer;
a first hard mask over the first gate spacer and the first dielectric layer; and
a second hard mask over the second gate spacer and the second dielectric layer, wherein the first hard mask and second hard mask have upper surfaces level with an upper surface of the third dielectric layer.
16. The device of claim 15 , wherein the first hard mask contacts a sidewall of the gate mask.
17. The device of claim 15 , wherein a thickness of the gate mask is greater than a thickness of the first dielectric layer.
18. The device of claim 15 , further comprising:
a conductive feature over and electrically coupled to the first source/drain, an upper surface of the conductive feature being level with an upper surface of the first hard mask.
19. The device of claim 18 , further comprising:
a fourth dielectric layer over the gate mask and the third dielectric layer; and
a contact extending through the fourth dielectric layer to the conductive feature, wherein the contact overlaps the first hard mask.
20. The device of claim 15 , wherein the first gate spacer contacts the gate mask.