IP Library › Granted Patent US 12,364,008
Granted Patent B2
US 12,364,008 · App. 17/903,922 · Granted Jul 15, 2025

Semiconductor device package and method of manufacturing the same

Inventors: Ming-Hung Chen (Kaohsiung, TW); Yung I Yeh (Kaohsiung, TW); Chang-Lin Yeh (Kaohsiung, TW); Sheng-Yu Chen (Kaohsiung, TW)
Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
H10D86/0214H01L25/0753H10D86/441H10D86/60H10H20/853H10H20/857H10H20/0362H10H20/0364
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 12,364,008
App. No.
17/903,922
Granted
Jul 15, 2025
Kind
B2
Abstract

A semiconductor device package includes a main substrate, at least one thin film transistor (TFT) module, at least one first electronic component, at least one encapsulant and a plurality of light emitting devices. The main substrate has a first surface and a second surface opposite to the first surface. The thin film transistor (TFT) module is disposed adjacent to and electrically connected to the first surface of the main substrate. The first electronic component is disposed adjacent to and electrically connected to the first surface of the main substrate. The encapsulant covers the at least one thin film transistor (TFT) module and the at least one first electronic component. The light emitting devices are electrically connected to the at least one thin film transistor (TFT) module.

Claims (21)

1. A semiconductor device package comprising:

a first circuit;

a driving circuit supported by the first circuit;

a package structure supported by the first circuit, comprising:

a first electronic component and a second electronic component partially overlapping the first electronic component along a first direction substantially perpendicular to a top surface of the first circuit;

a package substrate and a second encapsulant, the first electronic component is connected to the package substrate, and the second encapsulant encapsulates the package substrate and the first electronic component; and

a display device electrically connected to the package structure by the driving circuit, wherein the package structure is entirely disposed outside a projection of the display device along the first direction.

2. The semiconductor device package of claim 1 , wherein the display device includes a second circuit overlapping the first electronic component or the second electronic component along a second direction substantially parallel with the top surface of the first circuit.

3. A semiconductor device package comprising:

a display device;

a driving circuit disposed under the display device;

a first encapsulant encapsulating the driving circuit, wherein the driving circuit is spaced apart from the display device by the first encapsulant;

a first electronic component disposed near to the driving circuit, wherein the first electronic component is below the display device, and the first encapsulant does not contact the first electronic component;

a circuit supporting the driving circuit, the first electronic component and the display device; and

a package structure supported by the circuit, wherein the package structure comprises a package substrate, the first electronic component and a second encapsulant, the first electronic component is connected to the package substrate, and the second encapsulant encapsulates the package substrate and the first electronic component.

4. The semiconductor device package of claim 3 , wherein the display device includes a light emitting device and a protection layer covering the light emitting device, and the protection layer is free from overlapping the first electronic component in a direction substantially perpendicular to a top surface of the circuit.

5. The semiconductor device package of claim 1 , wherein the package structure further includes a third electronic component overlaps the display device and the second electronic component along a second direction substantially parallel with the top surface of the first circuit.

6. The semiconductor device package of claim 1 , wherein the package structure further includes a lower package body and an interconnection element, wherein the lower package body covers the first electronic component and a bottom surface of the package substrate, wherein the interconnection element extends through the lower package body and electrically connects the package substrate and the first circuit, wherein the interconnection element comprises a solder material disposed in the lower package body and tapering toward the package substrate, wherein the interconnection element includes a protrusion portion extending beyond the lower package body and tapering toward the first circuit.

7. The semiconductor device package of claim 1 , wherein the package structure further includes a lower package body and an interconnection element, wherein the lower package body covers the first electronic component and a bottom surface of the package substrate, wherein the interconnection element extends through the lower package body and electrically connects the package substrate and the first circuit, wherein the interconnection element overlaps the driving circuit along a second direction substantially parallel with the top surface of the first circuit.

8. The semiconductor device package of claim 1 , wherein a first gap is formed between the package structure and the display device, and a second gap is formed between the package structure and the first circuit, wherein the first gap is communicated with the second gap.

9. The semiconductor device package of claim 8 , wherein a width of the first gap is less than a width of the second gap.

Continuity (2)
Continuation 16557990 · Aug 30, 2019
Related Publication 20230005970A1 · Jan 5, 2023
References Cited (8)
US 8791474B1 · Bibl et al. · 2014 [cited by applicant]
US 20170005156A1 · Kim · 2017 [cited by examiner]
US 20170269749A1 · Bok · 2017 [cited by examiner]
US 20170278909A1 · Jeon et al. · 2017 [cited by applicant]
US 20200266180A1 · Pendse · 2020 [cited by examiner]
Final Office Action for U.S. Appl. No. 16/557,990, issued Feb. 1, 2022, 11 pages. [cited by applicant]
Non-Final Office Action for U.S. Appl. No. 16/557,990, issued Aug. 2, 2021, 11 pages. [cited by applicant]
Notice of Allowance for U.S. Appl. No. 16/557,990, issued May 2, 2022, 11 pages. [cited by applicant]