Limited lateral growth of S/D epi by outer dielectric layer in 3-dimensional stacked device
An integrated circuit includes a first semiconductor device and a second semiconductor device adjacent to the first semiconductor device. Each of the first and second semiconductor devices includes a lower transistor and an upper transistor on the lower transistor, and the upper and lower transistors each include a source region, a drain region, and a channel region extending between the source region and the drain region. The integrated circuit also includes a first dielectric spacer extending along an inner sidewall of the channel region of the upper and/or lower transistor of the first semiconductor device, a second dielectric spacer facing the first dielectric spacer and extending along an inner sidewall of the channel region of the upper and/or lower transistor of the second semiconductor device. The integrated circuit also includes an interconnect contact between the first semiconductor device and the second semiconductor device.
1. An integrated circuit comprising:
a first semiconductor device comprising:
a lower transistor; and
an upper transistor on the lower transistor, each of the lower transistor and the upper transistor comprises a source region, a drain region, and a channel region extending between the source region and the drain region; and
a second semiconductor device adjacent to the first semiconductor device, the second semiconductor device comprising:
a lower transistor; and
an upper transistor on the lower transistor, each of the lower transistor and the upper transistor comprises a source region, a drain region, and a channel region extending between the source region and the drain region;
a first dielectric spacer extending lengthwise along at least a portion of an inner sidewall of the channel region of at least one of the lower transistor and the upper transistor of the first semiconductor device;
a second dielectric spacer facing the first dielectric spacer and extending lengthwise along at least a portion of an inner sidewall of the channel region of at least one of the lower transistor and the upper transistor of the second semiconductor device; and
an interconnect contact between the first semiconductor device and the second semiconductor device.
2. The integrated circuit of claim 1 , wherein:
the first dielectric spacer extends along the inner sidewall of the channel region of both of the lower transistor and the upper transistor of the first semiconductor device, and
the second dielectric spacer extends along the inner sidewall of the channel of both of the lower transistor and the upper transistor of the second semiconductor device.
3. The integrated circuit of claim 1 , wherein:
the first dielectric spacer extends along the inner sidewall of the channel region of only the lower transistor of the first semiconductor device, and
the second dielectric spacer extends along the inner sidewall of the channel region of only the lower transistor of the second semiconductor device.
4. The integrated circuit of claim 1 , wherein:
the first dielectric spacer extends along the inner sidewall of region of only the upper transistor of the first semiconductor device, and
the second dielectric spacer extends along the inner sidewall of the channel region of only the upper transistor of the second semiconductor device.
5. The integrated circuit of claim 1 , further comprising:
a third dielectric spacer extending along an outer sidewall of the channel region of at least one of the lower transistor and the upper transistor of the first semiconductor device, and
a fourth dielectric spacer extending along an outer sidewall of region of at least one of the lower transistor and the upper transistor of the second semiconductor device.
6. The integrated circuit of claim 5 , wherein:
the third dielectric spacer extends along the outer sidewall of region of both the lower transistor and the upper transistor of the first semiconductor device, and
the fourth dielectric spacer extends along the outer sidewall of the channel region of at least one of the lower transistor and the upper transistor of the second semiconductor device.
7. The integrated circuit of claim 5 , wherein:
the third dielectric spacer extends along the outer sidewall of region of only the lower transistor of the first semiconductor device, and
the fourth dielectric spacer extends along the outer sidewall of the channel region of only the lower transistor of the second semiconductor device.
8. The integrated circuit of claim 5 , wherein:
the third dielectric spacer extends along the outer sidewall of the channel region of only the upper transistor of the first semiconductor device, and
the fourth dielectric spacer extends along the outer sidewall of the channel region of only the upper transistor of the second semiconductor device.
9. The integrated circuit of claim 5 , further comprising:
a fifth dielectric spacer extending along the inner sidewall of the channel region of the upper transistor of the first semiconductor device, and
a sixth dielectric spacer extending along the inner sidewall of the channel region of the upper transistor of the second semiconductor device.
10. The integrated circuit of claim 5 , further comprising:
a fifth dielectric spacer extending along the outer sidewall of the channel region of the upper transistor of the first semiconductor device, and
a sixth dielectric spacer extending along the outer sidewall of the channel region of the upper transistor of the second semiconductor device.
11. The integrated circuit of claim 1 , wherein, for each of the first semiconductor device and the second semiconductor device, the channel region of the lower transistor has a first length, and the channel region of the upper transistor has a second length less than the first length.
12. The integrated circuit of claim 1 , wherein, for each of the first semiconductor device and the second semiconductor device, region of the lower transistor and the channel region of the upper transistor have a same length.