Low latency memory access
A memory device includes receivers that use CMOS signaling levels (or other relatively large signal swing levels) on its command/address and data interfaces. The memory device also includes an asynchronous timing input that causes the reception of command and address information from the CMOS level receivers to be decoded and forwarded to the memory core (which is self-timed) without the need for a clock signal on the memory device's primary clock input. Thus, an activate row command can be received and initiated by the memory core before the memory device has finished exiting the low power state. Because the row operation is begun before the exit wait time has elapsed, the latency of one or more accesses (or other operations) following the exit from the low power state is reduced.
1. A memory component, comprising:
a memory core;
synchronous control circuitry to, based on the memory component being in a first mode, access the memory core in response to first command, first control, and first address information received via a first synchronous sampling of signals at a first set of links using a first timing signal received via a first synchronous timing reference interface; and
asynchronous control circuitry to, based on the memory component being in a second mode, access the memory core in response to second command, second control, and second address information received via an asynchronous sampling of signals at the first set of links and a second set of links using a second timing signal received via an asynchronous timing reference interface, the second set of links to communicate data bidirectionally when the memory component is in the first mode.
2. The memory component of claim 1 , wherein the asynchronous control circuitry is to activate a row in a bank of the memory core in response to the second command, second control, and second address information.
3. The memory component of claim 1 , wherein, in the first mode, information is to be communicated bidirectionally by the memory component, synchronously, via the second set of links, using a third timing signal received via a second synchronous timing reference interface.
4. The memory component of claim 1 , wherein, in the first mode, the asynchronous timing reference signal interface is to be synchronously sampled using the first timing signal.
5. The memory component of claim 1 , wherein a first synchronous interface that samples the first set of links synchronously using the first timing signal when in the first mode and a second synchronous interface that communicates synchronously with the second set of links using the third timing signal when in the first mode are not sampled synchronously using the first timing signal when in the second mode.
6. The memory component of claim 1 , wherein, while in the second mode and while the first timing signal is in an inactive signal, at least one transition of the third timing signal initiates the first asynchronous sampling of the first set of links to receive the second command, the second control, and the second address information.
7. The memory component of claim 4 , wherein the asynchronous timing reference signal interface is to be used, in the first mode, to receive a power control signal.
8. The memory component of claim 6 , wherein an exit from the second mode to the first mode is to be initiated by activating the first timing signal.
9. The memory component of claim 6 , wherein the at least one transition of the third timing signal initiates an exit from the second mode.
10. A method of operation within a memory component having a memory core, the method comprising:
based on the memory component being in a first mode, accessing the memory core in response to first command, first control, and first address information received via a first synchronous sampling of signals at a first set of links using a first timing signal received via a first synchronous timing reference interface; and
based on the memory component being in a second mode, accessing the memory core in response to second command, second control, and second address information received via an asynchronous sampling of signals at the first set of links and at a second set of links using a second timing signal received via an asynchronous timing reference interface, the second set of links communicating data bidirectionally when the memory component is in the first mode.
11. The method of claim 10 , further comprising activating a row in a bank of the memory core in response to the second command, second control, and second address information.
12. The method of claim 10 , further comprising, in the first mode, communicating information bidirectionally by the memory component, synchronously, via the second set of links, using a third timing signal received via a second synchronous timing reference interface.
13. The method of claim 10 , further comprising, in the first mode, synchronously sampling the asynchronous timing reference signal interface using the first timing signal.
14. The method of claim 10 , wherein, in the second mode, the first set of links and the second set of links are not sampled synchronously using the first timing signal.
15. The method of claim 10 , further comprising, initiating the first asynchronous sampling based at least one transition of the third timing signal to receive the second command, the second control, and the second address information while in the second mode and while the first timing signal is inactive.
16. The method of claim 15 , further comprising activating the first timing signal to initiate an exit from the second mode to the first mode.
17. The method of claim 15 , further comprising initiating an exit from the second mode based on the at least one transition of the third timing signal.
18. A memory component, comprising:
a memory core;
means for, based on the memory component being in a first mode, accessing the memory core in response to first command, first control, and first address information received via a first synchronous sampling of signals at a first set of links using a first timing signal received via a first synchronous timing reference interface; and
means for, based on the memory component being in a second mode, accessing the memory core in response to second command, second control, and second address information received via an asynchronous sampling of signals at the first set of links and a second set of links using a second timing signal received via an asynchronous timing reference interface, the second set of links to communicate data bidirectionally when the memory component is in the first mode.