IP Library › Granted Patent US 12,367,335
Granted Patent B1
US 12,367,335 · App. 17/809,899 · Granted Jul 22, 2025

Method and system to facilitate review of schematics for an electronic design

Inventor: Arnold Ginetti (Antibes, FR)
Assignee: Cadence Design Systems, Inc.
G06F30/398G06F30/12
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Quick Facts
Patent No.
US 12,367,335
App. No.
17/809,899
Granted
Jul 22, 2025
Kind
B1
Abstract

Disclosed is an improved approach to identify and visualize relevant changes that are made between an earlier schematic and an updated schematic. Both the old schematic and the updated schematic are presented into separate interface windows in conjunction with the layout design. Any changes between the schematics that are pertinent to the electronic design can be highlighted within the interface windows to permit the layout designer to properly appreciate any changes that are relevant to the layout.

Claims (33)

1. A computer implemented method implemented with a processor, the method comprising:

generating a user interface having a first portion for a first version of a schematic for an electronic design, a second portion for a second version of a schematic for the electronic design, and a third portion for a layout for the electronic design;

performing a layout versus schematic (LVS) analysis between the layout and the second version of the schematic for the electronic design;

receiving a selection that corresponds to a changed element identified by the LVS analysis; and

selectively highlighting the changed element in at least one of a first schematic view that displays the first version of the schematic or a second schematic view that displays the second version of the schematic.

2. The method of claim 1 , in which the first version of the schematic corresponds to a first configuration rule for a symbol in the schematic and the second version of the schematic corresponds to a second configuration rule for the symbol, wherein the symbol is resolved according to the second configuration rule before performing the LVS analysis.

3. The method of claim 2 , wherein the symbol is resolved according to the second configuration rule to associate the symbol with a sub-schematic.

4. The method of claim 1 , in which a first processing entity implements the first schematic view that displays the first version of the schematic and a second processing entity implements the second schematic view that displays the second version of the schematic.

5. The method of claim 4 , wherein the layout corresponds to the first version of the schematic, and both the first schematic view and the second schematic view are tied to the layout.

6. The method of claim 1 , wherein a list interface is displayed that visually presents the changed element in the list interface.

7. The method of claim 6 , wherein the changed element is identified in the list interface based at least upon operation of LVS (layout versus schematic) processing, and the list interface identifies at least one of an un-bound marker or an un-generated marker.

8. A computer program product embodied on a non-transitory computer readable medium, the non-transitory computer readable medium having stored thereon a sequence of instructions which, when executed by a processor causes the processor to execute a method, the method comprising:

generating a user interface having a first portion for a first version of a schematic for an electronic design, a second portion for a second version of a schematic for the electronic design, and a third portion for a layout for the electronic design;

performing a layout versus schematic (LVS) analysis between the layout and the second version of the schematic for the electronic design;

receiving a selection that corresponds to a changed element identified by the LVS analysis; and

selectively highlighting the changed element in at least one of a first schematic view that displays the first version of the schematic or a second schematic view that displays the second version of the schematic.

9. The computer program product of claim 8 , in which the first version of the schematic corresponds to a first configuration rule for a symbol in the schematic and the second version of the schematic corresponds to a second configuration rule for the symbol, wherein the symbol is resolved according to the second configuration rule before performing the LVS analysis.

10. The computer program product of claim 9 , wherein the symbol is resolved according to the second configuration rule to associate the symbol with a sub-schematic.

11. The computer program product of claim 8 , in which a first processing entity implements the first schematic view that displays the first version of the schematic and a second processing entity implements the second schematic view that displays the second version of the schematic.

12. The computer program product of claim 11 , wherein the layout corresponds to the first version of the schematic, and both the first schematic view and the second schematic view are tied to the layout.

13. The computer program product of claim 8 , wherein a list interface is displayed that visually presents the changed element in the list interface.

14. The computer program product of claim 13 , wherein the changed element is identified in the list interface based at least upon operation of LVS (layout versus schematic) processing, and the list interface identifies at least one of an un-bound marker or an un-generated marker.

15. A system, comprising:

a processor;

a memory for holding programmable code; and

wherein the programmable code includes instructions for generating a user interface having a first portion for a first version of a schematic for an electronic design, a second portion for a second version of a schematic for the electronic design, and a third portion for a layout for the electronic design; performing a layout versus schematic (LVS) analysis between the layout and the second version of the schematic for the electronic design;

receiving a selection that corresponds to a changed element identified by the LVS analysis; and selectively highlighting the changed element in at least one of a first schematic view that displays the first version of the schematic or a second schematic view that displays the second version of the schematic.

16. The system of claim 15 , in which the first version of the schematic corresponds to a first configuration rule for a symbol in the schematic and the second version of the schematic corresponds to a second configuration rule for the symbol, wherein the symbol is resolved according to the second configuration rule before performing the LVS analysis.

17. The system of claim 16 , wherein the symbol is resolved according to the second configuration rule to associate the symbol with a sub-schematic.

18. The system of claim 15 , in which a first processing entity implements the first schematic view that displays the first version of the schematic and a second processing entity implements the second schematic view that displays the second version of the schematic.

19. The system of claim 18 , wherein the layout corresponds to the first version of the schematic, and both the first schematic view and the second schematic view are tied to the layout.

20. The system of claim 15 , wherein a list interface is displayed that visually presents the changed element in the list interface.

21. The system of claim 20 , wherein the changed element is identified in the list interface based at least upon operation of LVS (layout versus schematic) processing, and the list interface identifies at least one of an un-bound marker or an un-generated marker.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2022
From: GINETTI, ARNOLD
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 060361/0308 →
References Cited (16)
US 10783292B1 · Clewes · 2020 [cited by examiner]
US 20110107281A1 · Sun · 2011 [cited by examiner]
Cadence, Cadence SiP Design, Connectivity-driven co-design and implementation of full system in package, Date identified for the document is from google.com is Jan. 2017. [cited by applicant]
Cadence, Orcad Capture, User's Guide, Second Edition, Dated May 2000. [cited by applicant]
Cadence, Lef/Def Language Reference, Product Version 5.7, Dated Nov. 2009. [cited by applicant]
Cadence Virtuoso Tutorial, Version 6.1, University of Southern California, EE209—Fall 2015, Last updated Oct. 2015. [cited by applicant]
Cadence, User's Guide for Virtuoso® Analog Design Environment, Product Version 5.1.41, Dated Sep. 2006. [cited by applicant]
Altium, “Differences”, Altium Documentation, Dated Jul. 2020. [cited by applicant]
Mitchell, B., “Novation Circuit Tracks vs Circuit—Worth The Upgrade?”, URL:https://wavelength.focuscamera.com/novation-circuit-worth-the-upgrade/, Dated Apr. 2021. [cited by applicant]
Glitch, D., “Review: Novation's Circuit Tracks is an even better Circuit groovebox” URL: https://djtechtools.com/2021/05/27/review-novations-circuit-tracks-is-an-even-better-circuit-groovebox/, Date identified for the d… [cited by applicant]
Jiang, J. et al., “Engineering Change Order for Combinational and Sequential Design Rectification”, Design, Automation And Test in Europe (DATE 2020), Dated 2020. [cited by applicant]
Krishnegowda, D., “A primer on engineering change order (ECO) using Conformal”, EDN, Design, IC Designer's Corner, Dated Nov. 2021. [cited by applicant]
Xilinx, Vivado Design Suite User Guide, Design Flows Overview, Vivado Design Suite, UG892 (v2022.1), Dated Apr. 2022. [cited by applicant]
Aras, User's Guide for Aras Innovator Product Engineering 14, Document #: 14.0.02021061201, dated Oct. 2021. [cited by applicant]
Mentor Graphics, PADS Layout Tutorial, Date identified for the document from google.com is Aug. 2017. [cited by applicant]
Non-Final Office Action for related U.S. Appl. No. 17/809,898 dated Mar. 21, 2025. [cited by applicant]