Automated analog layout
An automated analog layout tool creates not just one, but many electrically correct layouts from an input schematic. Designers can explore multiple layout options in a fraction of the time needed to produce just a single layout by hand. Because the tool produces layout results so quickly, parasitics are available for simulation early in the design process, further speeding the entire design cycle. The tool considers place and route concurrently.
1. A method comprising:
importing a first circuit schematic in a first format;
creating a first netlist from the first circuit schematic;
storing the first netlist in a memory;
using an electronic processor, automatically generating constraints for the first netlist, wherein the automatically generating constraints comprises:
providing a plurality of predefined patterns for a plurality of constraints,
reviewing the first netlist and identifying patterns in the first netlist that correspond to the predefined patterns associated with the constraints, and
when a predefined pattern is identified in the first netlist, using the constraint associated with that predefined pattern as one of the automatically generated constraints for the first netlist;
creating a second netlist by flattening the first netlist;
storing the second netlist in a memory;
importing a layout in a second format for parameterized cells associated with the second netlist;
evaluating the parameterized cells;
combining the second netlist and parameterized cells, generating one or more placed and routed layouts to obtain a polymorphic layout, wherein the generating comprises transforming the first circuit schematic into a layout for semiconductor manufacture via photolithography into the polymorphic layout; and
at least one of forming an integrated circuit comprising the polymorphic layout or creating at least one mask that is used for the fabrication of an integrated circuit comprising at least the polymorphic layout.
2. The method of claim 1 wherein a predefined pattern comprises at least one of a current mirror circuit, current mirror with differential pair circuit, a MOSFET capacitor, an operational amplifier circuit, a CMOS transmission gate, or a CMOS tristate inverter.
3. The method of claim 1 wherein the generating one or more placed and routed layouts to obtain a polymorphic layout comprises multiple placed and routed layouts.
4. The method of claim 1 comprising:
providing a graphical user interface comprising a first window and a second window;
in the first window, displaying the first circuit schematic for a first circuit; and
in the second window, displaying the one or more placed and routed layouts for the first circuit in the first window.
5. The method of claim 1 wherein the generating one or more placed and routed layouts to obtain a polymorphic layout comprises multiple placed and routed layouts, and the method comprises:
providing a graphical user interface comprising a first window and a second window;
in the first window, displaying the first circuit schematic for a first circuit; and
in the second window, displaying the multiple placed and routed layouts for the first circuit in the first window.
6. A method comprising:
providing a graphical user interface comprising a first window and a second window;
in the first window, displaying a first circuit schematic for a first circuit;
creating a first netlist from the first circuit schematic;
automatically generating constraints for the first netlist, wherein the automatically generating constraints comprises:
providing a plurality of predefined patterns for a plurality of constraints,
reviewing the first netlist and identifying patterns in the first netlist that correspond to the predefined patterns associated with the constraints, and
when a predefined pattern is identified in the first netlist, using the constraint associated with that predefined pattern as one of the automatically generated constraints for the first netlist;
using the first netlist, generating a plurality of layouts for the first circuit based on the automatically generated constraints for the first netlist;
in the second window, displaying the plurality of layouts for the first circuit in the first window, wherein each layout is a complete implementation of the first circuit comprising internal routing;
generating a first layout of the plurality of layouts, wherein the first layout is rectangular and comprises an X length and Y width; and
generating a second layout of the plurality of layouts, wherein the second layout is rectangular and comprises an X length and Y width, and relative to the first layout, structures and a routing of the second layout are arranged in a mirror image of those for the first layout;
at least one of creating at least one mask that is used for the fabrication of an integrated circuit, wherein the mask comprises at least one of the plurality of layouts for the first circuit, or forming an integrated circuit comprising at least one of the plurality of layouts for the first circuit.
7. The method of claim 6 comprising:
generating a third layout of the plurality of layouts, wherein the third layout is rectangular and comprises Y length and X width.
8. The method of claim 7 comprising:
generating a fourth layout of the plurality of layouts, wherein the fourth layout is rectangular and comprises Y length and X width, and relative to the third layout, structures and a routing of the fourth layout are arranged in a mirror image of those for the third layout.
9. The method of claim 6 comprising:
allowing a user to select one of the plurality of layouts for the first circuit as a layout in an integrated circuit design comprising the first circuit.
10. The method of claim 9
wherein the mask comprises at least the layout of the plurality of layouts for the first circuit that was selected by the user.
11. The method of claim 9 wherein
the integrated circuit formed comprises at least the layout of the plurality of layouts for the first circuit that was selected by the user.
12. The method of claim 6 wherein each layout comprises a transformation of the first circuit schematic into a layout for semiconductor manufacture via photolithography.