IP Library › Granted Patent US 12,505,276
Granted Patent B2
US 12,505,276 · App. 17/809,898 · Granted Dec 23, 2025

Method and system to facilitate schematics for an electronic design

Inventor: Arnold Ginetti (Antibes, FR)
Assignee: Cadence Design Systems, Inc.
G06F30/398G06F30/12
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Quick Facts
Patent No.
US 12,505,276
App. No.
17/809,898
Granted
Dec 23, 2025
Kind
B2
Abstract

Disclosed is a method and system for visualizing schematic changes for an electronic design, where multiple schematic view interfaces are provided such that a first schematic interface displays an older schematic version and a second schematic interface displays a newer schematic version. Coordination is performed between the multiple schematic views such that an element within any of the first or second schematic views is appropriately highlighted based upon a user input.

Claims (36)

1 . A computer implemented method implemented with a processor, the method comprising:

identifying a first version of a schematic for an electronic design;

identifying a second version of the schematic for the electronic design;

identifying a layout for the electronic design;

implementing a user interface having a first schematic view interface that displays the first version of the schematic, a second schematic view interface that displays the second version of the schematic, and a layout view that displays the layout of the electronic design;

receiving a selection that corresponds to a changed element in either or both of the first and second versions of the schematic; and

selectively highlighting the changed element in at least one of the first schematic view interface that displays the first version of the schematic or the second schematic view interface that displays the second version of the schematic.

2 . The method of claim 1 , in which a first processing entity implements the first schematic view interface that displays the first version of the schematic and a second processing entity implements the second schematic view interface that displays the second version of the schematic.

3 . The method of claim 2 , in which the first and second processing entities are implemented using a processing entity type that corresponds to at least one of a process, a thread, a virtual machine, or a container.

4 . The method of claim 2 , in which an inter-process communications mechanism is used to implement coordination between the first processing entity and the second processing entity.

5 . The method of claim 1 , wherein the layout corresponds to the first version of the schematic, and both the first schematic view interface and the second schematic view interface are tied to the layout.

6 . The method of claim 1 , wherein a list interface is displayed that visually presents the changed element in the list interface.

7 . The method of claim 6 , wherein the changed element is identified in the list interface based at least upon operation of LVS (layout versus schematic) processing, and the list interface identifies at least one of an un-bound marker or an un-generated marker.

8 . A computer program product embodied on a non-transitory computer readable medium having stored thereon a sequence of instructions which, when executed by a processor causes a set of acts comprising:

identifying a first version of a schematic for an electronic design;

identifying a second version of the schematic for the electronic design;

identifying a layout for the electronic design;

implementing a user interface having a first schematic view interface that displays the first version of the schematic, a second schematic view interface that displays the second version of the schematic, and a layout view that displays the layout of the electronic design;

receiving a selection that corresponds to a changed element in either or both of the first and second versions of the schematic; and

selectively highlighting the changed element in at least one of the first schematic view interface that displays the first version of the schematic or the second schematic view interface that displays the second version of the schematic.

9 . The computer program product of claim 8 , in which a first processing entity implements the first schematic view interface that displays the first version of the schematic and a second processing entity implements the second schematic view interface that displays the second version of the schematic.

10 . The computer program product of claim 9 , in which the first and second processing entities are implemented using a processing entity type that corresponds to at least one of a process, a thread, a virtual machine, or a container.

11 . The computer program product of claim 9 , in which an inter-process communications mechanism is used to implement coordination between the first processing entity and the second processing entity.

12 . The computer program product of claim 8 , wherein the layout corresponds to the first version of the schematic, and both the first schematic view interface and the second schematic view interface are tied to the layout.

13 . The computer program product of claim 8 , wherein a list interface is displayed that visually presents the changed element in the list interface.

14 . The computer program product of claim 13 , wherein the changed element is identified in the list interface based at least upon operation of LVS (layout versus schematic) processing, and the list interface identifies at least one of an un-bound marker or an un-generated marker.

15 . A system, comprising:

a processor;

a memory for holding a sequence of instructions; and

wherein the sequence of instructions includes instructions for identifying a first version of a schematic for an electronic design; identifying a second version of the schematic for the electronic design; identifying a layout for the electronic design; implementing a user interface having a first schematic view interface that displays the first version of the schematic, a second schematic view interface that displays the second version of the schematic, and a layout view that displays the layout of the electronic design; receiving a selection that corresponds to a changed element in either or both of the first and second versions of the schematic; and selectively highlighting the changed element in at least one of the first schematic view interface that displays the first version of the schematic or the second schematic view interface that displays the second version of the schematic.

16 . The system of claim 15 , in which a first processing entity implements the first schematic view interface that displays the first version of the schematic and a second processing entity implements the second schematic view interface that displays the second version of the schematic.

17 . The system of claim 16 , in which the first and second processing entities are implemented using a processing entity type that corresponds to at least one of a process, a thread, a virtual machine, or a container.

18 . The system of claim 16 , in which an inter-process communications mechanism is used to implement coordination between the first processing entity and the second processing entity.

19 . The system of claim 15 , wherein the layout corresponds to the first version of the schematic, and both the first schematic view interface and the second schematic view interface are tied to the layout.

20 . The system of claim 15 , wherein a list interface is displayed that visually presents the changed element in the list interface.

21 . The system of claim 20 , wherein the changed element is identified in the list interface based at least upon operation of LVS (layout versus schematic) processing, and the list interface identifies at least one of an un-bound marker or an un-generated marker.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 30, 2022
From: GINETTI, ARNOLD
To: CADENCE DESIGN SYSTEMS, INC.
Reel/Frame 060361/0239 →
Continuity (1)
Related Publication 20240005081A1 · Jan 4, 2024
References Cited (17)
US 10783292B1 · Clewes et al. · 2020 [cited by applicant]
US 20110107281A1 · Sun · 2011 [cited by examiner]
Cadence, Cadence SiP Design, Connectivity-driven co-design and implementation of full system in package, Date identified for the document is from google.com is Jan. 2017. [cited by applicant]
Cadence, Orcad Capture, User's Guide, Second Edition, Dated May 2000. [cited by applicant]
Cadence, LEF/DEF Language Reference, Product Version 5.7, Dated Nov. 2009. [cited by applicant]
Cadence Virtuoso Tutorial, Version 6.1, University of Southern California, EE209—Fall 2015, Last updated Oct. 2015. [cited by applicant]
Cadence, User's Guide for Virtuoso® Analog Design Environment, Product Version 5.1.41, Dated Sep. 2006. [cited by applicant]
Altium, “Differences”, Altium Documentation, Dated Jul. 2020. [cited by applicant]
Mitchell, B., “Novation Circuit Tracks vs Circuit—Worth The Upgrade?”, URL:https://wavelength.focuscamera.com/novation-circuit-tracks-vs-circuit-worth-the-upgrade/, Dated Apr. 2021. [cited by applicant]
Glitch, D., “Review: Novation's Circuit Tracks is an even better Circuit groovebox” URL: https://djtechtools.com/2021/05/27/review-novations-circuit-tracks-is-an-even-better-circuit-groovebox/, Date identified for the d… [cited by applicant]
Jiang, J. et al, “Engineering Change Order for Combinational and Sequential Design Rectification”, Design, Automation And Test in Europe (DATE 2020), Dated 2020. [cited by applicant]
Krishnegowda, D., “A primer on engineering change order (ECO) using Conformal”, EDN, Design, IC Designer's Corner, Dated Nov. 2021. [cited by applicant]
Xilinx, Vivado Design Suite User Guide, Design Flows Overview, Vivado Design Suite, UG892 (v2022.1), Dated Apr. 2022. [cited by applicant]
Aras, User's Guide for Aras Innovator Product Engineering 14, Document #: 14.0.02021061201, dated Oct. 2021. [cited by applicant]
Mentor Graphics, PADS Layout Tutorial, Date identified for the document from google.com is Aug. 2017. [cited by applicant]
Non-Final Office Action dated Dec. 10, 2024 for U.S. Appl. No. 17/809,899. [cited by applicant]
Notice of Allowance dated Mar. 20, 2025 for U.S. Appl. No. 17/809,899. [cited by applicant]