IP Library Granted Patent US 12,373,626
Granted Patent B2
US 12,373,626 · App. 17/719,332 · Granted Jul 29, 2025

Method and non-transitory computer readable medium

Inventors: Tsun-Yu Yang (Changhua County, TW); Ren-Hong Fu (Taipei, TW); Chin-Cheng Kuo (Taoyuan, TW); Jui-Feng Kuan (Hsinchu County, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
G06F30/392G06F30/31G06F30/3308
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Quick Facts
Patent No.
US 12,373,626
App. No.
17/719,332
Granted
Jul 29, 2025
Kind
B2
Abstract

A method is disclosed herein. The method includes: connecting a first number of elements in an integrated circuit (IC); parameterizing, by a processor, the first number into first parameters; generating, by the processor, second parameters of the IC based on the first parameters; and adjusting the IC based on the second parameters.

Claims (69)

1. A method, comprising:

connecting a first number of elements in an integrated circuit (IC);

parameterizing, by a processor, the first number into first parameters;

generating, by the processor, second parameters of the IC based on the first parameters;

adjusting the IC based on the second parameters;

triggering an application programming interface (API) to adjust the first parameters into the second parameters; and

executing the API to update a netlist of the IC according to the second parameters.

2. The method of claim 1 , wherein connecting the first number of elements comprises:

connecting the first number of elements in parallel.

3. The method of claim 1 , further comprising:

executing a simulation of the IC; and

in response to the simulation being executed, adjusting the first parameters into the second parameters.

4. The method of claim 3 , further comprising:

when the first parameters are adjusted into the second parameters, obtaining factors related to a performance of the IC corresponding to the second parameters;

adjusting the netlist of the IC according to the factors and the second parameters; and

changing the factors when the netlist is adjusted.

5. The method of claim 1 , further comprising:

parameterizing, by the processor, widths and lengths of the first number of elements into the first parameters; and

writing the widths and the lengths into the netlist of the IC.

6. The method of claim 1 , further comprising:

parameterizing, by the processor, widths and lengths of the first number of elements into the first parameters.

7. The method of claim 1 , further comprising:

sweeping the first parameters;

comparing a performance of the swept first parameters with a predetermined performance;

when the performance is higher than the predetermined performance, annotating the swept first parameters to be optimal parameters; and

restructuring the IC according to the optimal parameters.

8. The method of claim 7 , further comprising:

updating a schematic based on the optimal parameters;

before sweeping the first parameters, executing the schematic including the first parameters; and

after updating the schematic, generating a layout based on the schematic.

9. A non-transitory computer readable medium, comprising computer executable instructions for carrying out a method, the method comprising:

stacking a first number of transistors in an integrated circuit (IC);

parameterizing the first number into first parameters;

generating second parameters of the IC based on the first parameters; and

adjusting the IC based on the second parameters.

10. The non-transitory computer readable medium of claim 9 , wherein the method further comprising:

representing dimensions of the transistors by the first parameters, to perform a simulation of the IC.

11. The non-transitory computer readable medium of claim 10 , wherein the method further comprises:

sweeping the first parameters;

comparing a performance of the swept first parameters with a predetermined performance; and

when the performance is higher than the predetermined performance, generating a layout based on the simulation corresponding to the performance.

12. The non-transitory computer readable medium of claim 10 , wherein the method further comprises:

in response to the simulation, adjusting the first parameters into the second parameters.

13. The non-transitory computer readable medium of claim 12 , wherein the method further comprises:

when the first parameters are adjusted into the second parameters, obtaining factors related to a performance of the IC corresponding to the second parameters;

adjusting a netlist of the IC according to the factors and the second parameters; and

changing the factors when the netlist is adjusted.

14. The non-transitory computer readable medium of claim 9 , wherein the method further comprises:

connecting the transistors in parallel.

15. The non-transitory computer readable medium of claim 14 , wherein the method further comprises:

parameterizing widths and lengths of the transistors into the first parameters.

16. A method, comprising:

designing an integrated circuit (IC) including a first number of transistors which are coupled in parallel with each other;

generating, by a processor, first parameters corresponding to connection configurations of the transistors and the first number;

adjusting, by the processor, the first parameters to generate second parameters; and

performing, by the processor, a simulation of the IC according to the second parameters.

17. The method of claim 16 , further comprising:

sweeping, by the processor, the first parameters;

comparing, by the processor, a performance of the swept first parameters with a predetermined performance; and

when the performance is higher than the predetermined performance, generating a layout based on the simulation corresponding to the performance.

18. The method of claim 17 , further comprising:

in response to the simulation, adjusting, by the processor, the first parameters into the second parameters.

19. The method of claim 18 , further comprising:

when the first parameters are adjusted into the second parameters, obtaining, by the processor, factors related to the performance corresponding to the second parameters;

adjusting, by the processor, a netlist of the IC according to the factors and the second parameters; and

changing, by the processor, the factors when the netlist is adjusted.

20. The method of claim 19 , further comprising:

sweeping, by the processor, the netlist; and

comparing, by the processor, the performance of the swept netlist with the predetermined performance.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 15, 2022
From: YANG, TSUN-YU; FU, REN-HONG; KUO, CHIN-CHENG; KUAN, JUI-FENG
To: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Reel/Frame 059615/0703 →
Continuity (3)
Continuation 16693027 · Nov 22, 2019
Provisional Application 62773004 · Nov 29, 2018
Related Publication 20220237360A1 · Jul 28, 2022
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