Method and non-transitory computer readable medium of operating an electronic design automation platform for an optimal intgrated circuit design

1. A method, comprising:

adjusting, by a processor, first parameters associated with parameterized cells in a netlist of an integrated circuit (IC) to generate second parameters associated with the parameterized cells in the netlist of the IC,

wherein at least one of the first parameters and at least one of second parameters correspond to a number of a plurality of elements that are coupled to each other in the parameterized cells and correspond to connection configurations of the plurality of elements;

updating, by the processor, the parameterized cells according to the second parameters;

updating, by the processor, the netlist of the IC according to the parameterized cells being updated; and

performing a simulation according to the netlist of the IC.

2. The method of claim 1 , wherein the plurality of elements include a plurality of transistors of a circuit in the netlist of the IC, and

the plurality of transistors are coupled in parallel.

3. The method of claim 1 , wherein updating the netlist of the IC comprises:

updating parameters of a circuit in the netlist of the IC.

4. The method of claim 1 , further comprising:

obtaining a layout dependence effect according to the netlist of the IC which is adjusted;

wherein the parameterized cells are further updated according to the layout dependence effect.

5. The method of claim 1 , wherein updating the netlist of the IC comprises:

comparing a performance of the netlist of the IC with a predetermined performance; and

if the performance of the netlist of the IC is higher than the predetermined performance, updating the netlist of the IC.

6. The method of claim 5 , wherein performing the simulation according to the netlist of the IC comprises:

performing the simulation according to the netlist of the IC whose performance is higher than the predetermined performance.

7. The method of claim 1 , further comprising:

generating a layout based on the simulation; and

based on the layout, fabricating at least one component in a semiconductor device.

8. A non-transitory computer readable medium, comprising computer executable instructions for carrying out a method, the method comprising:

adjusting first parameters associated with parameterized cells in a netlist of an integrated circuit (IC) to generate second parameters associated with the parameterized cells in the netlist of the IC,

wherein at least one of the first parameters and at least one of second parameters correspond to a number of a plurality of transistors that are stacked in the parameterized cells and correspond to connection configurations of the plurality of transistors;

updating the netlist of the IC according to the second parameters; and

performing a simulation according to the netlist of the IC.

9. The non-transitory computer readable medium of claim 8 , wherein updating the netlist of the IC according to the second parameters comprises:

updating at least one element of a circuit in the netlist of the IC.

10. The non-transitory computer readable medium of claim 8 , wherein updating the netlist of the IC according to the second parameters comprises:

updating parameters of a circuit in the netlist of the IC.

11. The non-transitory computer readable medium of claim 8 , further comprising:

obtaining a layout dependence effect according to the netlist of the IC which is adjusted.

12. The non-transitory computer readable medium of claim 11 , wherein updating the netlist of the IC according to the second parameters comprises:

updating the netlist of the IC according to the second parameters and the layout dependence effect.

13. The non-transitory computer readable medium of claim 8 , wherein updating the netlist of the IC according to the second parameters comprises:

comparing a performance of the netlist of the IC with a predetermined performance; and

if the performance of the netlist of the IC is higher than the predetermined performance, updating the netlist of the IC according to the second parameters.

14. A method, comprising:

before performing a simulation according to a netlist of an integrated circuit (IC), adjusting, by a processor, first parameters, being initial parameters, to generate second parameters associated with parameterized cells in the netlist of the IC,

wherein at least one of the first parameters and at least one of second parameters correspond to a number of a plurality of transistors included in at least one element in the parameterized cells and correspond to connection configurations of the plurality of transistors;

updating, by the processor, the netlist of the IC according to the second parameters; and

performing, by the processor, a simulation according to the netlist.

15. The method of claim 14 , wherein updating the netlist of the IC comprises:

updating the at least one element of a circuit in the netlist of the IC.

16. The method of claim 14 , wherein updating the netlist of the IC comprises:

updating parameters of a circuit in the netlist of the IC.

17. The method of claim 14 , wherein updating the netlist of the IC comprises:

comparing a performance of the netlist of the IC with a predetermined performance; and

when the performance of the netlist of the IC is higher than the predetermined performance, updating the netlist of the IC.

18. The method of claim 17 , wherein performing the simulation according to the netlist of the IC comprises:

performing the simulation according to the netlist of the IC whose performance is higher than the predetermined performance.

19. The method of claim 17 , wherein updating the netlist of the IC comprises:

before the comparing, sweeping the second parameters associated with the parameterized cells in the netlist.

20. The method of claim 14 , wherein updating the netlist of the IC comprises:

sweeping a circuit structure in the netlist of the IC;

comparing a performance of the netlist of the IC with a predetermined performance; and

when the performance of the netlist of the IC is higher than the predetermined performance, updating the netlist of the IC.