Display device
A display device is disclosed that includes a pixel circuit, a light emitting element, and a driving circuit. The pixel circuit includes a plurality of pixel transistors. The light emitting element is electrically connected to the pixel circuit. The driving circuit is configured to provide a prescribed signal to the pixel circuit and includes a plurality of driving transistors. A gate signal is applied to a gate of at least one transistor among the plurality of pixel transistors and the plurality of driving transistors. The gate signal includes a first interval in which a DC signal is applied and a second interval in which an AC signal is applied. The second interval includes a first sub-interval in which a first voltage is applied and a second sub-interval in which a second voltage different from the first voltage is applied. The first voltage is a negative voltage and the second voltage is a positive voltage or about 0 V.
1. A display device comprising:
a pixel circuit comprising a plurality of pixel transistors;
a light emitting element electrically connected to the pixel circuit; and
a driving circuit configured to provide a prescribed signal to the pixel circuit, and comprising a plurality of driving transistors,
wherein a gate signal is applied to a gate of at least one transistor among the plurality of pixel transistors and the plurality of driving transistors,
the gate signal comprises a first interval in which a DC signal is applied and a second interval in which an AC signal is applied,
the second interval comprises a first sub-interval in which a first voltage is applied and a second sub-interval in which a second voltage different from the first voltage is applied, and
the first voltage is a negative voltage and the second voltage is a positive voltage or about 0 V.
2. The display device of claim 1 ,
wherein the driving circuit comprises a plurality of driving stages, the plurality of driving stages each comprising a clock terminal configured to receive a clock signal and an output terminal configured to output a signal to the pixel circuit, and
the at least one transistor is electrically connected to the clock terminal to receive the clock signal, and the clock signal is the gate signal.
3. The display device of claim 2 , wherein a voltage of the DC signal is a positive voltage having a same magnitude as the first voltage, and the second voltage is about 0 V.
4. The display device of claim 1 , wherein the pixel circuit is electrically connected to an initialization scan line, a compensation scan line, a write scan line, and an emission signal line, and
the driving circuit provides an initialization scan signal to the initialization scan line, a compensation scan signal to the compensation scan line, a write scan signal to the write scan line, and an emission control signal to the emission signal line.
5. The display device of claim 4 , wherein the gate signal is one of the initialization scan signal, the compensation scan signal, the write scan signal, and the emission control signal.
6. The display device of claim 1 , wherein a voltage of the DC signal is a positive voltage having a same magnitude as the first voltage.
7. The display device of claim 1 , wherein a duty ratio of the second interval is about 90% or greater.
8. The display device of claim 1 , wherein the at least one transistor is an oxide thin-film transistor.
9. The display device of claim 1 , wherein the at least one transistor is an amorphous indium-gallium-zinc oxide transistor.
10. The display device of claim 1 , wherein the at least one transistor is an N-type thin-film transistor.
11. The display device of claim 1 , wherein, when the second voltage is about 0 V, a duty ratio of the second sub-interval is about 0.01% to about 75%.
12. The display device of claim 1 , wherein, when the first voltage is about −20 V to about −10 V and the second voltage is a positive voltage having a same magnitude as the first voltage, a duty ratio of the second sub-interval is about 0.01% to about 50%.
13. The display device of claim 1 , wherein, when the first voltage is about −30V or higher and smaller than about −20V and the second voltage is a positive voltage having a same magnitude as the first voltage, a duty ratio of the second sub-interval is about 0.01% to about 30%.
14. An electronic device comprising comprising:
a pixel circuit comprising a plurality of pixel transistors;
a light emitting element electrically connected to the pixel circuit;
scan lines comprising an initialization scan line, a compensation scan line, and a write scan line that are electrically connected to the pixel circuit; and
a driving circuit configured to provide a prescribed signal to the pixel circuit, and comprising a plurality of driving transistors,
wherein a gate signal is applied to a gate of an oxide thin-film transistor among the plurality of pixel transistors and the plurality of driving transistors,
the gate signal comprises a first interval in which a DC signal is applied and a second interval in which an AC signal is applied,
the second interval comprises a first sub-interval in which a first voltage is applied and a second sub-interval in which a second voltage different from the first voltage is applied, and
a duty ratio of the second sub-interval is about 0.01% to about 75%.
15. The electronic device of claim 14 ,
wherein the driving circuit comprises a plurality of driving stages, the plurality of driving stages each comprising a clock terminal configured to receive a clock signal and an output terminal configured to output a signal to the pixel circuit, and
the oxide thin-film transistor is electrically connected to the clock terminal to receive the clock signal, and the clock signal is the gate signal.
16. The electronic device of claim 14 , further comprising an emission signal line that is electrically connected to the pixel circuit,
wherein the driving circuit provides an initialization scan signal to the initialization scan line, a compensation scan signal to the compensation scan line, a write scan signal to the write scan line, and an emission control signal to the emission signal line, and
the gate signal is one of the initialization scan signal, the compensation scan signal, the write scan signal, and the emission control signal.
17. The electronic device of claim 14 , wherein, when the first voltage is about −30 V to about −10 V and the second voltage is about 0 V, a duty ratio of the second sub-interval is about 0.01% to about 75%.
18. The electronic device of claim 14 , wherein, when the first voltage is about −20 V to about −10 V and the second voltage is a positive voltage having a same magnitude as the first voltage, a duty ratio of the second sub-interval is about 0.01% to about 50%.
19. The electronic device of claim 14 , wherein, when the first voltage is about −30V or higher and smaller than about −20V and the second voltage is a positive voltage having a same magnitude as the first voltage, a duty ratio of the second sub-interval is about 0.01% to about 30%.
20. The electronic device of claim 14 , wherein the oxide thin-film transistor is an N-type thin-film transistor.