Circuit topology for high performance memory with secondary pre-charge transistor
Embodiments herein relate to a memory device in which a secondary pre-charge transistor is coupled to each bit line in an array of memory cells. A column select transistor such as an nMOS is between the secondary pre-charge transistor such as a pMOS and a power supply node. The secondary pre-charge transistor and the column select transistor have their control gates connected so that they are controlled by a common control signal. The secondary pre-charge transistor prevents floating of the bit line voltage in a read operation and maintains a voltage of the bit line in a specified range.
1. An apparatus, comprising:
a column of memory cells coupled to a bit line;
a primary pre-charge transistor coupled to the bit line;
a secondary pre-charge transistor coupled to the bit line; and
a column select transistor coupled to the bit line between the primary pre-charge transistor and the secondary pre-charge transistor, wherein a control gate of the secondary pre-charge transistor is connected to a control gate of the column select transistor.
2. The apparatus of claim 1 , wherein:
the secondary pre-charge transistor comprises a source coupled to the bit line and a drain at ground.
3. The apparatus of claim 2 , wherein:
the column select transistor is an nMOS transistor and the secondary pre-charge transistor is a pMOS transistor; and
the nMOS transistor comprises a drain coupled to the primary pre-charge transistor (PP) and a source coupled to the bit line.
4. The apparatus of claim 3 , wherein:
in a read operation of a memory cell of the column of memory cells, the pMOS transistor is to hold its source at a voltage level between Vthp and Vdd−Vthn, where Vthp is a threshold voltage of the pMOS transistor, Vthn is a threshold voltage of the nMOS transistor, and Vdd is a voltage provided by the primary pre-charge transistor.
5. The apparatus of claim 1 , wherein:
the secondary pre-charge transistor is to prevent floating of a voltage of the bit line during a read operation of a memory cell of the column of memory cells.
6. The apparatus of claim 1 , wherein:
the column is in a set of columns and the column select transistor is to receive a select signal when the column is selected in the set of columns for a read operation.
7. The apparatus of claim 1 , wherein:
the column is in a set of columns;
each column in the set of columns is coupled to a respective bit line;
the primary pre-charge transistor is coupled to each respective bit line;
a respective secondary pre-charge transistor is coupled to each respective bit line;
a respective column select transistor is coupled to each respective bit line between the primary pre-charge transistor and the respective secondary pre-charge transistor; and
for each respective bit line, a control gate of the respective secondary pre-charge transistor is coupled to a control gate of the respective column select transistor.
8. The apparatus of claim 1 , further comprising:
a set of word lines, wherein each memory cell comprises a control gate coupled to a respective word line in the set of word lines, a drain coupled to the bit line, and a source coupled to ground.
9. The apparatus of claim 1 , wherein the memory cells comprise read-only memory (ROM) cells.
10. The apparatus of claim 1 , wherein:
the column select transistor and the secondary pre-charge transistor are commonly controlled by a column select signal.
11. An apparatus, comprising:
a column of memory cells coupled to a bit line;
an nMOS column select transistor coupled to the bit line and to a pre-charge node;
a pMOS transistor coupled to the bit line and to ground;
the nMOS column select transistor is to allow a pre-charge of the bit line from the pre-charge node in a first phase of a read operation and a discharge of the bit line in a second phase of the read operation, the second phase follows the first phase; and
the pMOS transistor is to maintain a voltage of the bit line in a specified range during the first and second phases of the read operation.
12. The apparatus of claim 11 , wherein:
a control gate of the pMOS transistor is coupled to a control gate of the nMOS column select transistor.
13. The apparatus of claim 11 , wherein:
the specified range is between Vthp and Vdd−Vthn, where Vthp is a threshold voltage of the pMOS transistor, Vthn is a threshold voltage of the nMOS column select transistor, and Vdd is a power supply voltage of a primary pre-charge transistor.
14. The apparatus of claim 11 , wherein:
the pMOS transistor is to prevent floating of a voltage of the bit line during the first and second phases of the read operation.
15. The apparatus of claim 11 , wherein:
the bit line is among a plurality of respective bit lines;
the plurality of respective bit lines are coupled to the pre-charge node;
a respective nMOS column select transistor is coupled to each respective bit line and to the pre-charge node;
a respective pMOS transistor is coupled to each respective bit line and to ground; and
for each respective bit line, the respective nMOS column select transistor has a control gate coupled to a control gate of the respective pMOS transistor to receive a common control signal.