Non-destructive mode cache programming in NAND flash memory devices
A memory device includes memory cells arranged in rows and columns, each memory cell configured to store n-bit of data, where n is a whole number larger than two, and a periphery circuit coupled to the memory cells and configured to program selected memory cells according to n logic pages of current programming data. The periphery circuit includes page buffers, and each page buffer includes latches. The periphery circuit is configured to store the n logic pages of the current programming data in the latches for programming the selected memory cells, release one or more of the latches, by discarding one or more of the n logic pages of the current programming data correspondingly, before the programming the selected memory cells according to the n logic pages of the current programming data is completed, and store one of n logic pages of next programming data in one or more of the latches before the programming the selected memory cells according to the n logic pages of the current programming data is completed.
1. A memory device, comprising:
memory cells arranged in rows and columns, each memory cell configured to store n-bit of data, where n is a whole number larger than two; and
a periphery circuit coupled to the memory cells and configured to program selected memory cells according to n logic pages of current programming data, wherein:
the periphery circuit comprises page buffers, each page buffer comprising latches; and
the periphery circuit is configured to:
store the n logic pages of the current programming data in the latches for programming the selected memory cells;
release one or more of the latches, by discarding one or more of the n logic pages of the current programming data correspondingly, before the programming the selected memory cells according to the n logic pages of the current programming data is completed; and
store one of n logic pages of next programming data in one or more of the latches before the programming the selected memory cells according to the n logic pages of the current programming data is completed.
2. The memory device of claim 1 , wherein:
the latches comprise n data latches and a cache latch; and
the periphery circuit is further configured to:
release one or more of the n data latches, by discarding one or more of the n logic pages of the current programming data correspondingly, before the programming the selected memory cells according to the n logic pages of the current programming data is completed; and
store one of n logic pages of next programming data in the cache latch before the programming the selected memory cells according to the n logic pages of the current programming data is completed.
3. The memory device of claim 2 , wherein the peripheral circuit is further configured to release a first data latch of the n data latches, by discarding a first logic page of the current programming data after states P 1 , P 2 , . . . , P(2 n-1 ) of the selected memory cells have passed programming verification.
4. The memory device of claim 3 , wherein the peripheral circuit is further configured to:
transfer data from the cache latch to the first data latch after discarding the first logic page of the current programming data; and
store a first logic page of the next programming data in the cache latch.
5. The memory device of claim 3 , wherein the peripheral circuit is further configured to recover the first logic page of the current programming data by separating the 2 n logic states into two groups using a read reference voltage V R2 n-1 , wherein:
the read reference voltage V R2 n-1 is higher than a threshold voltage of state P(2 n-1 −1), but lower than a threshold voltage of state P(2 n-1 ); and
the logic states in each group are distinct based on the remaining logic pages of the current programming data and the mapping scheme.
6. The memory device of claim 4 , wherein the peripheral circuit is further configured to release a second data latch of the n data latches, by discarding a second logic page of the current programming data after states P 1 , P 2 , . . . , and P(2 n-1 +2 n-2 ) of the selected memory cells have passed programming verification.
7. The memory device of claim 6 , wherein the peripheral circuit is further configured to:
transfer the first logic page of the next programming data from the cache latch to the second data latch after discarding the second logic page of the current programming data; and
store a second logic page of the next programming data in the cache latch.
8. The memory device of claim 7 , wherein the peripheral circuit is further configured to release a third data latch, by discarding a third logic page of the current programming data after states P 1 , P 2 , . . . , and P(2 n −2) of the selected memory cells have passed programming verification.
9. The memory device of claim 8 , wherein the peripheral circuit is further configured to:
transfer the second logic page of the next programming data from the cache latch to the third data latch after discarding the third logic page of the current programming data; and
store a third logic page of the next programming data in the cache latch.
10. The memory device of claim 9 , wherein the peripheral circuit is further configured to release a fourth data latch, by discarding a fourth logic page of the current programming data after states P 1 , P 2 , . . . , and P(2 n −1) of the selected memory cells have passed programming verification.
11. The memory device of claim 10 , wherein the peripheral circuit is further configured to:
transfer the third logic page of the next programming data from the cache latch to the fourth data latch or a latch SL of the page buffer after discarding the fourth logic page of the current programming data; and
store a fourth logic page of the next programming data in the cache latch.
12. The memory device of claim 6 , wherein the peripheral circuit is further configured to release a third data latch, by discarding a third logic page of the current programming data after states P 1 , P 2 , . . . , and P(2 n −1) of the selected memory cells have passed programming verification.
13. The memory device of claim 12 , wherein the peripheral circuit is further configured to:
transfer the second logic page of the next programming data from the cache latch to the third data latch or a latch SL of the page buffer after discarding the third logic page of the current programming data; and
store a third logic page of the next programming data in the cache latch.
14. The memory device of claim 1 , wherein the peripheral circuit is further configured to recover the discarded one or more of the n logic pages of the current programing data when there is a programming failure, based on remaining logic pages of the current programming data, logic states of the selected memory cells that have passed programming verification and a mapping scheme between a set of n-bit binary codes and 2 n logic states of each memory cell.
15. A method of cache programming for a memory device comprising memory cells arranged in rows and columns, the method comprising:
storing n logic pages of current programming data in page buffers, where n is a whole number greater than 1, each page buffer comprising latches;
programming a selected memory cells according to the n logic pages of current programming data;
discarding one or more of the n logic pages of the current programming data before the programming the selected memory cells according to the n logic pages of the current programming data is completed; and
storing one of n logic pages of next programming data before the programming the selected memory cells according to the n logic pages of the current programming data is completed.
16. The method of claim 15 , further comprising:
after discarding the one or more of the n logic pages of current programming data, programming the selected memory cells based on remaining logic pages of current programming data.
17. The method of claim 15 , further comprising:
recovering the discarded one or more of the n logic pages of the current programming data when there is a programming failure.
18. The method of claim 15 , further comprising:
storing at least one logic page of the next programming data before the programming the selected memory cells according to the n logic pages of the current programming data is completed.
19. A memory system, comprising:
a memory device comprising:
memory cells arranged in rows and columns, each memory cell configured to store n-bit of data, where n is a whole number larger than 1; and
a periphery circuit coupled to the memory cells and configured to program selected memory cells according to n logic pages of current programming data, wherein:
the periphery circuit comprises page buffers, each page buffer comprising latches; and
the periphery circuit is configured to:
store the n logic pages of the current programming data in the latches for programming the selected memory cells;
release one or more of the latches, by discarding one or more of the n logic pages of the current programming data correspondingly, before the programming the selected memory cells according to the n logic pages of the current programming data is completed; and
store one of n logic pages of next programming data in one or more of the latches before the programming the selected memory cells according to the n logic pages of the current programming data is completed; and
a memory controller coupled to the memory device and configured to control the memory device.
20. The memory system of claim 19 , wherein:
the latches comprise n data latches and a cache latch; and
the periphery circuit is further configured to:
release one or more of the n data latches, by discarding one or more of the n logic pages of the current programming data correspondingly, before the programming the selected memory cells according to the n logic pages of the current programming data is completed; and
store one of n logic pages of next programming data in the cache latch before the programming the selected memory cells according to the n logic pages of the current programming data is completed.