Semiconductor memory device
The present disclosure provides a semiconductor memory device. The semiconductor memory device includes a peripheral circuit structure on a semiconductor substrate, a conductive line connected to the peripheral circuit structure, a peripheral circuit side bonding conductive pattern connected to the conductive line, a peripheral circuit side auxiliary bonding conductive pattern spaced apart from the peripheral circuit side bonding conductive pattern, a cell array side bonding conductive pattern contacting the peripheral circuit side bonding conductive pattern, a cell array side auxiliary bonding conductive pattern contacting the peripheral circuit side auxiliary bonding conductive pattern, and a memory cell array connected to the cell array side bonding conductive pattern.
1. A semiconductor memory device comprising:
a peripheral circuit structure disposed in a semiconductor substrate and a first array layer over the semiconductor substrate;
a conductive line disposed in a second array layer, wherein the second array layer is over the first array layer, and wherein the conductive line is connected to the peripheral circuit structure;
a peripheral circuit side bonding conductive pattern disposed in a third array layer, wherein the third array layer is over the second array layer, and wherein the peripheral circuit side bonding conductive pattern is connected to the conductive line;
a peripheral circuit side auxiliary bonding conductive pattern disposed in the third array layer, the peripheral circuit side auxiliary bonding conductive pattern spaced apart from the peripheral circuit side bonding conductive pattern;
a cell array side bonding conductive pattern disposed in a fourth array layer, the fourth array layer over the third array layer, the cell array side bonding conductive pattern contacting the peripheral circuit side bonding conductive pattern;
a cell array side auxiliary bonding conductive pattern disposed in the fourth array layer, the cell array side auxiliary bonding conductive pattern contacting the peripheral circuit side auxiliary bonding conductive pattern; and
a memory cell array disposed over the fourth array layer, the memory cell array connected to the cell array side bonding conductive pattern.
2. The semiconductor memory device of claim 1 , further comprising:
a first insulating layer disposed in the second array layer and penetrated by the conductive line;
a first bonding insulating layer between the peripheral circuit side bonding conductive pattern and the peripheral circuit side auxiliary bonding conductive pattern; and
a second bonding insulating layer between the cell array side bonding conductive pattern and the cell array side auxiliary bonding conductive pattern.
3. The semiconductor memory device of claim 2 , wherein the peripheral circuit side auxiliary bonding conductive pattern overlaps the first insulating layer and is spaced apart from the conductive line of the second array layer.
4. The semiconductor memory device of claim 1 , wherein the memory cell array comprises:
a plurality of conductive patterns spaced apart from each other and stacked over the fourth array layer;
a channel structure passing through the plurality of conductive patterns; and
a memory layer between each of the plurality of conductive patterns and the channel structure.
5. The semiconductor memory device of claim 4 , wherein the cell array side bonding conductive pattern forms a bit line connected to the channel structure,
the peripheral circuit structure includes a first transistor having a junction formed in the semiconductor substrate, and
the junction of the first transistor is electrically connected to the bit line via the conductive line and the peripheral circuit side bonding conductive pattern.
6. The semiconductor memory device of claim 4 , further comprising:
a conductive gate contact extending from one of the plurality of conductive patterns toward the fourth array layer.
7. The semiconductor memory device of claim 6 , wherein the cell array side bonding conductive pattern forms a connection pattern connected to the conductive gate contact,
the peripheral circuit structure includes a second transistor having a junction formed in the semiconductor substrate, and
the junction of the second transistor is electrically connected to the conductive gate contact via the conductive line, the peripheral circuit side bonding conductive pattern, and the connection pattern.
8. A semiconductor memory device comprising:
a semiconductor substrate having an upper surface, the upper surface extending in a horizontal direction and facing a vertical direction;
a memory cell array including a gate stack, the gate stack including a plurality of conductive patterns spaced apart from each other in the vertical direction, the memory cell array stacked over the semiconductor substrate;
a channel structure extending to pass through the plurality of conductive patterns;
a memory layer between the channel structure and the gate stack;
a plurality of peripheral circuit side bonding conductive patterns included in a first bonding array layer and a plurality of peripheral circuit side auxiliary bonding conductive patterns included in the first bonding array layer, the plurality of peripheral circuit side bonding conductive patterns spaced apart from the plurality of peripheral circuit side auxiliary bonding conductive patterns, wherein the first bonding array layer is between the memory cell array and the semiconductor substrate;
a plurality of cell array side bonding conductive patterns included in a second bonding array layer and a plurality of cell array side auxiliary bonding conductive patterns included in the second bonding array layer, the plurality of cell array side bonding conductive patterns spaced apart from the plurality of cell array side auxiliary bonding conductive patterns, wherein the second bonding array layer is between the first bonding array layer and the memory cell array; and
a plurality of conductive lines disposed between the first bonding array layer and the semiconductor substrate and respectively connected to the plurality of peripheral circuit side bonding conductive patterns.
9. The semiconductor memory device of claim 8 , wherein the plurality of cell array side bonding conductive patterns are in direct contact with the plurality of peripheral circuit side bonding conductive patterns, and
the plurality of cell array side auxiliary bonding conductive patterns are in direct contact with the plurality of peripheral circuit side auxiliary bonding conductive patterns.
10. The semiconductor memory device of claim 8 ,
wherein the plurality of peripheral circuit side auxiliary bonding conductive patterns are spaced apart from the cell array side bonding conductive patterns,
wherein the plurality of peripheral circuit side auxiliary bonding conductive patterns are spaced apart from the plurality of conductive lines, and
wherein the plurality of cell array side auxiliary bonding conductive patterns are spaced apart from the peripheral circuit side bonding conductive patterns.
11. The semiconductor memory device of claim 8 , further comprising:
a first bonding insulating layer disposed in the first bonding array layer, the first bonding insulating layer penetrated by the plurality of peripheral circuit side bonding conductive patterns and the plurality of peripheral circuit side auxiliary bonding conductive patterns;
a first insulating layer extending along one surface of the first bonding insulating layer facing the semiconductor substrate and one surface of each of the plurality of peripheral circuit side auxiliary bonding conductive patterns, and disposed between the plurality of conductive lines;
a second bonding insulating layer disposed in the second bonding array layer, the second bonding insulating layer penetrated by the plurality of cell array side bonding conductive patterns and the plurality of peripheral circuit side auxiliary bonding conductive patterns; and
a second insulating layer extending along one surface of the second bonding insulating layer facing the memory cell array and one surface of each of the cell array side auxiliary bonding conductive patterns.
12. The semiconductor memory device of claim 8 , further comprising:
a first transistor and a second transistor disposed under the plurality of conductive lines,
wherein each of the first transistor and the second transistor includes a gate insulating layer and a gate electrode stacked on the semiconductor substrate, and junctions defined in the semiconductor substrate on both sides of the gate electrode.
13. The semiconductor memory device of claim 12 ,
wherein the plurality of conductive lines include a first conductive line connected to the junction of the first transistor and a second conductive line connected to the junction of the second transistor, and
the plurality of cell array side bonding conductive patterns includes a bit line connected to the channel structure and a plurality of connection patterns connected to each of the plurality of conductive patterns.